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Simplify branch_op/slt_op signals

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Olof Kindgren 2021-10-08 22:15:55 +02:00
parent 9d3ebf3e96
commit 9c4bdd4bfe
3 changed files with 12 additions and 12 deletions
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10
rtl/serv_decode.v
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@ -15,7 +15,7 @@ module serv_decode
output reg o_ebreak,
output reg o_branch_op,
output reg o_shift_op,
output reg o_slt_op,
output reg o_slt_or_branch,
output reg o_rd_op,
output reg o_two_stage_op,
output reg o_dbus_en,
@ -80,8 +80,8 @@ module serv_decode
~opcode[2] | (funct3[0] & ~funct3[1] & ~opcode[0] & ~opcode[4]) |
(funct3[1] & ~funct3[2] & ~opcode[0] & ~opcode[4]) | co_mdu_op;
wire co_shift_op = op_or_opimm & (funct3[1:0] == 2'b01) & !co_mdu_op;
wire co_slt_op = op_or_opimm & (funct3[2:1] == 2'b01) & !co_mdu_op;
wire co_branch_op = opcode[4] & !opcode[2];
wire co_slt_or_branch = (opcode[4] | (funct3[1] & opcode[2]) | (imm30 & opcode[2] & opcode[3] & ~funct3[2])) & !co_mdu_op;
wire co_branch_op = opcode[4];
wire co_dbus_en = ~opcode[2] & ~opcode[4];
wire co_mtval_pc = opcode[4];
wire co_mem_word = funct3[1];
@ -259,7 +259,7 @@ module serv_decode
o_ebreak = co_ebreak;
o_branch_op = co_branch_op;
o_shift_op = co_shift_op;
o_slt_op = co_slt_op;
o_slt_or_branch = co_slt_or_branch;
o_rd_op = co_rd_op;
o_mdu_op = co_mdu_op;
o_ext_funct3 = co_ext_funct3;
@ -321,7 +321,7 @@ module serv_decode
o_mtval_pc <= co_mtval_pc;
o_branch_op <= co_branch_op;
o_shift_op <= co_shift_op;
o_slt_op <= co_slt_op;
o_slt_or_branch <= co_slt_or_branch;
o_rd_op <= co_rd_op;
o_mdu_op <= co_mdu_op;
o_ext_funct3 <= co_ext_funct3;

8
rtl/serv_state.v
View file

@ -35,7 +35,7 @@ module serv_state
input wire i_branch_op,
input wire i_shift_op,
input wire i_sh_right,
input wire i_slt_op,
input wire i_slt_or_branch,
input wire i_e_op,
input wire i_rd_op,
//MDU
@ -90,10 +90,10 @@ module serv_state
//Prepare RF for writes when everything is ready to enter stage two
// and the first stage didn't cause a misalign exception
assign o_rf_wreq = !misalign_trap_sync &
((i_shift_op & (i_sh_done | !i_sh_right) & !o_cnt_en & init_done) |
assign o_rf_wreq = !misalign_trap_sync & !o_cnt_en & init_done &
((i_shift_op & (i_sh_done | !i_sh_right)) |
i_dbus_ack | (MDU & i_mdu_ready) |
(stage_two_req & (i_slt_op | i_branch_op)));
i_slt_or_branch);
assign o_dbus_cyc = !o_cnt_en & init_done & i_dbus_en & !i_mem_misalign;

6
rtl/serv_top.v
View file

@ -83,7 +83,7 @@ module serv_top
wire ebreak;
wire branch_op;
wire shift_op;
wire slt_op;
wire slt_or_branch;
wire rd_op;
wire mdu_op;
@ -208,7 +208,7 @@ module serv_top
.i_branch_op (branch_op),
.i_shift_op (shift_op),
.i_sh_right (sh_right),
.i_slt_op (slt_op),
.i_slt_or_branch (slt_or_branch),
.i_e_op (e_op),
.i_rd_op (rd_op),
//MDU
@ -244,7 +244,7 @@ module serv_top
.o_ebreak (ebreak),
.o_branch_op (branch_op),
.o_shift_op (shift_op),
.o_slt_op (slt_op),
.o_slt_or_branch (slt_or_branch),
.o_rd_op (rd_op),
.o_sh_right (sh_right),
.o_mdu_op (mdu_op),