Add support for DECA Max 10 board

README.md

@@ -142,7 +142,13 @@ FPGA Pin D11 (Connector JP1, pin 38) is used for UART output with 57600 baud rat
 
     fusesoc run --target=de0_nano servant
 
-### SoCKit development board
+### DECA development kit
+
+FPGA Pin W18 (Pin 3 P8 connector)  is used for UART output with 57600 baud rate. Key 0 is reset and Led 0 q output.
+
+    fusesoc run --target=deca servant
+
+### SoCKit development kit
 
 FPGA Pin F14 (HSTC GPIO addon connector J2, pin 2) is used for UART output with 57600 baud rate. 
 

data/deca.sdc

@@ -0,0 +1,8 @@
+# Main system clock (50 Mhz)
+create_clock -name "clk" -period 20.000ns [get_ports {i_clk}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty

data/deca.tcl

@@ -0,0 +1,19 @@
+#MAX10_CLK2_50  3.3V
+set_location_assignment PIN_P11 -to i_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
+
+#LED[0]
+set_location_assignment PIN_C7 -to q
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q
+
+#P8 3 GPIO0_D0    (P8 1 GND)
+set_location_assignment PIN_W18 -to uart_txd
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_txd
+
+#KEY[0]
+set_location_assignment PIN_H21 -to i_rst_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n
+
+#  Configuration mode that allows Memory Initialisation
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM"
+

servant.core

@@ -52,9 +52,16 @@ filesets:
     files:
       - data/sockit.sdc : {file_type : SDC}
       - data/sockit.tcl : {file_type : tclSource}
-      - servant/servive_clock_gen_sockit.v : {file_type : verilogSource}
+      - servant/servive_clock_gen.v : {file_type : verilogSource}
       - servant/servive.v : {file_type : verilogSource}
-      
+
+  deca:
+    files:
+      - data/deca.sdc : {file_type : SDC}
+      - data/deca.tcl : {file_type : tclSource}
+      - servant/servive_clock_gen.v : {file_type : verilogSource}
+      - servant/servive.v : {file_type : verilogSource}
+
   de0_nano:
     files:
       - data/de0_nano.sdc : {file_type : SDC}
@@ -144,6 +151,7 @@ targets:
 
   sockit:
     default_tool : quartus
+    description: SoCKit development kit by Arrow / Terasic
     filesets : [mem_files, soc, sockit]
     parameters : [memfile, memsize]
     tools:
@@ -151,7 +159,18 @@ targets:
         family : CycloneV
         device : 5CSXFC6D6F31C6
     toplevel: servive
-    
+
+  deca:
+    default_tool : quartus
+    description: DECA development kit by Arrow / Terasic
+    filesets : [mem_files, soc, deca]
+    parameters : [memfile, memsize]
+    tools:
+      quartus:
+        family : MAX 10
+        device : 10M50DAF484C6GES
+    toplevel: servive
+   
   de0_nano:
     default_tool : quartus
     filesets : [mem_files, soc, de0_nano]

servant/servive_clock_gen_sockit.v

@@ -1,34 +0,0 @@
-`default_nettype none
-module servive_clock_gen
-  (input wire i_clk,
-   input wire i_rst,
-   output wire o_clk,
-   output wire o_rst);
-
-   wire        locked;
-   reg [9:0]   r;
-
-   assign o_rst = r[9];
-
-   always @(posedge o_clk)
-     if (locked)
-       r <= {r[8:0],1'b0};
-     else
-       r <= 10'b1111111111;
-
-   wire [5:0] 	  clk;
-
-   assign 	  o_clk = clk[0];
-
-   altpll
-     #(.operation_mode         ("NORMAL"),
-       .clk0_divide_by         (25),
-       .clk0_multiply_by       (8),
-       .inclk0_input_frequency (20000))
-   pll
-     (.areset       (i_rst),
-      .inclk        ({1'b0, i_clk}),
-      .clk          (clk),
-      .locked       (locked));
-
-endmodule