Inline adders

rtl/ser_add.v

@@ -1,25 +0,0 @@
-`default_nettype none
-module ser_add
-  (
-   input wire  clk,
-   input wire  rst,
-   input wire  a,
-   input wire  b,
-   input wire  clr,
-   output wire q,
-   output wire o_v);
-
-   reg 	       c_r;
-
-   wire axorb = a^b;
-
-   assign o_v = (axorb & c_r) | (a&b);
-
-   assign q   = axorb ^ c_r;
-   always @(posedge clk)
-     if (rst)
-       c_r <= 1'b0;
-     else
-       c_r <= !clr & o_v;
-
-endmodule

rtl/serv_alu.v

@@ -36,7 +36,13 @@ module serv_alu
    reg         en_r;
    wire        shamt_ser;
    wire        plus_1;
+
+   wire        add_cy;
+   reg 	       add_cy_r;
+
    wire        b_inv_plus_1;
+   wire        b_inv_plus_1_cy;
+   reg 	       b_inv_plus_1_cy_r;
 
    wire op_b = i_op_b_rs2 ? i_rs2 : i_imm;
    assign shamt_ser = i_sh_right ? op_b : b_inv_plus_1;
@@ -61,33 +67,9 @@ module serv_alu
       .i_d (i_buf),
       .o_q (result_sh));
 
-   wire        b_inv_plus_1_cy;
-
-   always @(posedge clk)
-     if (i_shamt_en)
-       shamt_msb <= b_inv_plus_1_cy;
-
-   ser_add ser_add_inv_plus_1
-     (
-      .clk (clk),
-      .rst (i_rst),
-      .a   (~op_b),
-      .b   (plus_1),
-      .clr (!i_en),
-      .q   (b_inv_plus_1),
-      .o_v (b_inv_plus_1_cy));
-
-   wire       add_b = i_sub ? b_inv_plus_1 : op_b;
-
-   ser_add ser_add
-     (
-      .clk (clk),
-      .rst (i_rst),
-      .a   (i_rs1),
-      .b   (add_b),
-      .clr (!i_en),
-      .q   (result_add),
-      .o_v ());
+   wire add_b = i_sub ? b_inv_plus_1 : op_b;
+   assign {add_cy,result_add}   = i_rs1+add_b+add_cy_r;
+   assign {b_inv_plus_1_cy,b_inv_plus_1} = {1'b0,~op_b}+plus_1+b_inv_plus_1_cy_r;
 
    ser_lt ser_lt
      (
@@ -113,11 +95,17 @@ module serv_alu
    reg 	eq_r;
 
    always @(posedge clk) begin
+      add_cy_r <= i_en & add_cy;
+      b_inv_plus_1_cy_r <= i_en & b_inv_plus_1_cy;
+
       if (i_en) begin
 	 result_lt_r <= result_lt;
       end
       eq_r <= result_eq | ~i_en;
       en_r <= i_en;
+
+      if (i_shamt_en)
+	shamt_msb <= b_inv_plus_1_cy;
    end
 
    assign result_eq = eq_r & (i_rs1 == op_b);

rtl/serv_ctrl.v

@@ -30,7 +30,11 @@ module serv_ctrl
    reg 	      en_pc_r;
 
    wire       pc_plus_4;
+   wire       pc_plus_4_cy;
+   reg 	      pc_plus_4_cy_r;
    wire       pc_plus_offset;
+   wire       pc_plus_offset_cy;
+   reg 	      pc_plus_offset_cy_r;
    wire       pc_plus_offset_aligned;
    wire       plus_4;
 
@@ -46,15 +50,7 @@ module serv_ctrl
    assign o_ibus_adr[0] = pc;
    assign o_bad_pc = pc_plus_offset_aligned;
 
-   ser_add ser_add_pc_plus_4
-     (
-      .clk (clk),
-      .rst (i_rst),
-      .a   (pc),
-      .b   (plus_4),
-      .clr (i_cnt_done),
-      .q   (pc_plus_4),
-      .o_v ());
+   assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r;
 
    shift_reg
      #(
@@ -75,22 +71,16 @@ module serv_ctrl
 
    assign offset_a = i_pc_rel & pc;
    assign offset_b = i_utype ? (i_imm & (i_cnt[4] | (i_cnt[3:2] == 2'b11))): i_buf;
-
-   ser_add ser_add_pc_plus_offset
-     (
-      .clk (clk),
-      .rst (i_rst),
-      .a   (offset_a),
-      .b   (offset_b),
-      .clr (!i_pc_en),
-      .q   (pc_plus_offset),
-      .o_v ());
+   assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r;
 
    assign pc_plus_offset_aligned = pc_plus_offset & en_pc_r;
 
    assign o_ibus_cyc = en_pc_r & !i_pc_en;
 
    always @(posedge clk) begin
+      pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy;
+      pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy;
+
       if (i_pc_en)
 	en_pc_r <= 1'b1;
       else if (o_ibus_cyc & i_ibus_ack)

serv.core

@@ -7,7 +7,6 @@ filesets:
     files:
       - rtl/serv_params.vh : {is_include_file : true}
       - rtl/shift_reg.v
-      - rtl/ser_add.v
       - rtl/ser_lt.v
       - rtl/ser_shift.v
       - rtl/serv_bufreg.v