add support for SoCKit development kit board

data/sockit.sdc

@@ -0,0 +1,8 @@
+# Main system clock (50 Mhz)
+create_clock -name "clk" -period 20.000ns [get_ports {i_clk}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty

data/sockit.tcl

@@ -0,0 +1,11 @@
+set_location_assignment PIN_AF14 -to i_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
+
+set_location_assignment PIN_AF10 -to q
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q
+
+set_location_assignment PIN_F14 -to uart_txd
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_txd
+
+set_location_assignment PIN_AE9 -to i_rst_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n

servant.core

@@ -48,6 +48,13 @@ filesets:
       - servant/servclone10_clock_gen.v : {file_type : verilogSource}
       - servant/servclone10.v : {file_type : verilogSource}
 
+  sockit:
+    files:
+      - data/sockit.sdc : {file_type : SDC}
+      - data/sockit.tcl : {file_type : tclSource}
+      - servant/servive_clock_gen_sockit.v : {file_type : verilogSource}
+      - servant/servive.v : {file_type : verilogSource}
+      
   de0_nano:
     files:
       - data/de0_nano.sdc : {file_type : SDC}
@@ -135,6 +142,16 @@ targets:
         device : 10CL025YU256C8G
     toplevel : servclone10
 
+  sockit:
+    default_tool : quartus
+    filesets : [mem_files, soc, sockit]
+    parameters : [memfile, memsize]
+    tools:
+      quartus:
+        family : CycloneV
+        device : 5CSXFC6D6F31C6
+    toplevel: servive
+    
   de0_nano:
     default_tool : quartus
     filesets : [mem_files, soc, de0_nano]

servant/servive_clock_gen_sockit.v

@@ -0,0 +1,34 @@
+`default_nettype none
+module servive_clock_gen
+  (input wire i_clk,
+   input wire i_rst,
+   output wire o_clk,
+   output wire o_rst);
+
+   wire        locked;
+   reg [9:0]   r;
+
+   assign o_rst = r[9];
+
+   always @(posedge o_clk)
+     if (locked)
+       r <= {r[8:0],1'b0};
+     else
+       r <= 10'b1111111111;
+
+   wire [5:0] 	  clk;
+
+   assign 	  o_clk = clk[0];
+
+   altpll
+     #(.operation_mode         ("NORMAL"),
+       .clk0_divide_by         (25),
+       .clk0_multiply_by       (8),
+       .inclk0_input_frequency (20000))
+   pll
+     (.areset       (i_rst),
+      .inclk        ({1'b0, i_clk}),
+      .clk          (clk),
+      .locked       (locked));
+
+endmodule