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add support for machdyne kolibri
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4
data/machdyne_kolibri.pcf
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4
data/machdyne_kolibri.pcf
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@ -0,0 +1,4 @@
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set_io clk48 G1
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set_io led B11
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set_io tx B1
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set_io rx B2
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@ -133,6 +133,15 @@ Pin 9 is used for UART output with 57600 baud rate.
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iceprog build/servant_1.2.1/icestick-icestorm/servant_1.2.1.bin
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iceprog build/servant_1.2.1/icestick-icestorm/servant_1.2.1.bin
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Machdyne Kolibri
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^^^^^^^^^^^^^^^^
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Pin B1 is used for UART output with 115200 baud rate. The serial port on Kolibri is accessible as a USB-CDC device.
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fusesoc run --target=machdyne_kolibri servant
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ldprog -Ks build/servant_1.2.1/machdyne_kolibri-icestorm/servant_1.2.1.bin
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Nandland Go Board
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Nandland Go Board
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^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^
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17
servant.core
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servant.core
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@ -142,6 +142,11 @@ filesets:
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- servant/servant_lx9.v : {file_type : verilogSource}
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- servant/servant_lx9.v : {file_type : verilogSource}
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- data/lx9_microboard.ucf : {file_type : UCF}
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- data/lx9_microboard.ucf : {file_type : UCF}
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machdyne_kolibri:
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files:
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- servant/servant_md_kolibri.v : {file_type : verilogSource}
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- data/machdyne_kolibri.pcf : {file_type : PCF}
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nexys_2:
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nexys_2:
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files:
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files:
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- servant/servax_clock_gen.v : {file_type : verilogSource}
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- servant/servax_clock_gen.v : {file_type : verilogSource}
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@ -399,6 +404,18 @@ targets:
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speed : -2
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speed : -2
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toplevel : servant_lx9
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toplevel : servant_lx9
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machdyne_kolibri:
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default_tool: icestorm
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description : Machdyne Kolibri FPGA Dongle
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filesets : [mem_files, soc, machdyne_kolibri]
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parameters : [memfile, memsize]
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tools:
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tools:
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icestorm:
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nextpnr_options : [--hx4k, --package, bg121, --freq, 48]
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pnr: next
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toplevel : servant_md_kolibri
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nexys_2_500:
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nexys_2_500:
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default_tool: ise
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default_tool: ise
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filesets : [mem_files, soc, nexys_2]
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filesets : [mem_files, soc, nexys_2]
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46
servant/servant_md_kolibri.v
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servant/servant_md_kolibri.v
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// based on servant_upduino2.v
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`default_nettype none
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module servant_md_kolibri
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(
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input wire clk48,
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output wire led,
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output wire tx);
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parameter memfile = "zephyr_hello.hex";
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parameter memsize = 8192;
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wire clk32;
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wire locked;
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reg rst = 1'b1;
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// 48MHz -> 32MHz
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0010), // DIVR = 2
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.DIVF(7'b0111111), // DIVF = 63
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.DIVQ(3'b101), // DIVQ = 5
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.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
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) uut (
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.LOCK(locked),
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(clk48),
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.PLLOUTCORE(clk32)
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);
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always @(posedge clk32)
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rst <= !locked;
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servant
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#(.memfile (memfile),
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.memsize (memsize))
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servant
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(.wb_clk (clk32),
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.wb_rst (rst),
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.q (tx));
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assign led = tx;
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endmodule
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