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Fix CSR width issues in debug module
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This commit is contained in:
Olof Kindgren 2024-10-17 14:34:08 +02:00
parent 9bf8672fb2
commit cd60abe837
1 changed files with 2 additions and 2 deletions
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4
rtl/serv_debug.v
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@ -52,7 +52,7 @@ module serv_debug
input wire i_ibus_ack,
input wire [4:0] i_rd_addr,
input wire i_cnt_en,
input wire i_csr_in,
input wire [B:0] i_csr_in,
input wire i_csr_mstatus_en,
input wire i_csr_mie_en,
input wire i_csr_mcause_en,
@ -149,7 +149,7 @@ module serv_debug
end
if (i_cnt_en)
dbg_csr <= {i_csr_in, dbg_csr[31:1]};
dbg_csr <= {i_csr_in, dbg_csr[31:W]};
if (update_rd)
if (i_csr_mstatus_en)
dbg_mstatus <= dbg_csr;