Add ECP5 evaluation board target

Done by analogy with ulx3s target

data/ecp5_evn.lpf

@@ -0,0 +1,16 @@
+# 12MHz clock from FTDI FT2232H
+LOCATE COMP "clk" SITE "A10";
+IOBUF PORT "clk" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk" 12 MHZ;
+
+# SW4 button
+LOCATE COMP "nreset" SITE "P4";
+IOBUF PORT "nreset" IO_TYPE=LVCMOS33;
+
+# LED0
+LOCATE COMP "led0" SITE "A13";
+IOBUF PORT "led0" IO_TYPE=LVCMOS25;
+
+# J40 Header Pin #1
+LOCATE COMP "uart_txd" SITE "K2";
+IOBUF PORT "uart_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;

servant.core

@@ -128,6 +128,13 @@ filesets:
       - servant/servix_ebaz4205.v : {file_type : verilogSource}
       - data/ebaz4205.xdc : {file_type : xdc}
 
+  ecp5_evn:
+    files:
+      - data/ecp5_evn.lpf : {file_type : LPF}
+      - servant/ecp5_evn_pll.v : {file_type : verilogSource}
+      - servant/servant_ecp5_evn_clock_gen.v : {file_type : verilogSource}
+      - servant/servant_ecp5_evn.v : {file_type : verilogSource}
+
   go_board:
     files:
       - data/go_board.pcf : {file_type : PCF}
@@ -349,6 +356,16 @@ targets:
       vivado: {part : xc7z010clg400-1}
     toplevel : servix_ebaz4205
 
+  ecp5_evn:
+    default_tool: trellis
+    description : ECP5 evaluation board
+    filesets : [mem_files, soc, ecp5_evn]
+    parameters : [memfile, memsize]
+    tools:
+      trellis:
+        nextpnr_options : [--package, CABGA381, --um5g-85k]
+    toplevel: servant_ecp5_evn
+
   go_board:
     default_tool : icestorm
     filesets : [mem_files, soc, go_board]

servant/ecp5_evn_pll.v

@@ -0,0 +1,48 @@
+// generated with "ecppll -n ecp5_evn_pll -i 12 -o 16 --clkin_name clki --clkout0_name clko -f ecp5_evn_pll.v"
+
+// diamond 3.7 accepts this PLL
+// diamond 3.8-3.9 is untested
+// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
+// cause of this could be from wrong CPHASE/FPHASE parameters
+module ecp5_evn_pll
+(
+    input clki, // 12 MHz, 0 deg
+    output clko, // 16 MHz, 0 deg
+    output locked
+);
+(* FREQUENCY_PIN_CLKI="12" *)
+(* FREQUENCY_PIN_CLKOP="16" *)
+(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
+EHXPLLL #(
+        .PLLRST_ENA("DISABLED"),
+        .INTFB_WAKE("DISABLED"),
+        .STDBY_ENABLE("DISABLED"),
+        .DPHASE_SOURCE("DISABLED"),
+        .OUTDIVIDER_MUXA("DIVA"),
+        .OUTDIVIDER_MUXB("DIVB"),
+        .OUTDIVIDER_MUXC("DIVC"),
+        .OUTDIVIDER_MUXD("DIVD"),
+        .CLKI_DIV(3),
+        .CLKOP_ENABLE("ENABLED"),
+        .CLKOP_DIV(37),
+        .CLKOP_CPHASE(18),
+        .CLKOP_FPHASE(0),
+        .FEEDBK_PATH("CLKOP"),
+        .CLKFB_DIV(4)
+    ) pll_i (
+        .RST(1'b0),
+        .STDBY(1'b0),
+        .CLKI(clki),
+        .CLKOP(clko),
+        .CLKFB(clko),
+        .CLKINTFB(),
+        .PHASESEL0(1'b0),
+        .PHASESEL1(1'b0),
+        .PHASEDIR(1'b1),
+        .PHASESTEP(1'b1),
+        .PHASELOADREG(1'b1),
+        .PLLWAKESYNC(1'b0),
+        .ENCLKOP(1'b0),
+        .LOCK(locked)
+	);
+endmodule

servant/servant_ecp5_evn.v

@@ -0,0 +1,31 @@
+`default_nettype none
+module servant_ecp5_evn
+(
+ input wire  clk,
+ input wire nreset,
+ output wire led0,
+ output wire uart_txd);
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+
+   wire      wb_clk;
+   wire      wb_rst;
+
+   assign led0 = nreset;
+
+   servant_ecp5_evn_clock_gen clock_gen
+     (.i_clk (clk),
+      .i_rst (!nreset),
+      .o_clk (wb_clk),
+      .o_rst (wb_rst));
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (wb_clk),
+      .wb_rst (wb_rst),
+      .q      (uart_txd));
+
+endmodule

servant/servant_ecp5_evn_clock_gen.v

@@ -0,0 +1,25 @@
+`default_nettype none
+module servant_ecp5_evn_clock_gen
+  (
+   input  i_clk,
+   input  i_rst,
+   output o_clk,
+   output o_rst);
+
+   wire   locked;
+
+   reg [1:0] rst_reg;
+   always @(posedge o_clk)
+     if (i_rst)
+       rst_reg <= 2'b11;
+     else
+       rst_reg <= {!locked, rst_reg[1]};
+
+   assign o_rst = rst_reg[0];
+
+   ecp5_evn_pll pll
+     (.clki   (i_clk),
+      .clko   (o_clk),
+      .locked (locked));
+
+endmodule