xilinx PLL: allows to specify PLL output frequency (16 or 32 MHz)

servant.core

@@ -75,7 +75,7 @@ targets:
   nexys_a7:
     default_tool: vivado
     filesets : [mem_files, soc, nexys_a7]
-    parameters : [memfile, memsize]
+    parameters : [memfile, memsize, frequency=32]
     tools:
       vivado: {part : xc7a100tcsg324-1}
     toplevel : servix
@@ -110,6 +110,11 @@ parameters:
     description : Preload RAM with a hex file at runtime (overrides memfile)
     paramtype : plusarg
 
+  frequency:
+    datatype    : int
+    description : PLL output frequency
+    paramtype   : vlogparam
+
   memfile:
     datatype    : file
     description : Preload RAM with a hex file at compile-time

servant/servix.v

@@ -4,6 +4,7 @@ module servix
  input wire  i_clk,
  output wire q);
 
+   parameter frequency = 32;
    parameter memfile = "zephyr_hello.hex";
    parameter memsize = 8192;
    parameter PLL = "NONE";
@@ -11,7 +12,9 @@ module servix
    wire      wb_clk;
    wire      wb_rst;
 
-   servix_clock_gen clock_gen
+   servix_clock_gen
+     #(.frequency (frequency))
+   clock_gen
      (.i_clk (i_clk),
       .o_clk (wb_clk),
       .o_rst (wb_rst));

servant/servix_clock_gen.v

@@ -4,6 +4,8 @@ module servix_clock_gen
    output wire o_clk,
    output reg  o_rst);
 
+   parameter frequency = 32;
+
    wire   clkfb;
    wire   locked;
    reg 	  locked_r;
@@ -12,7 +14,7 @@ module servix_clock_gen
      #(.BANDWIDTH("OPTIMIZED"),
        .CLKFBOUT_MULT(16),
        .CLKIN1_PERIOD(10.0), //100MHz
-       .CLKOUT0_DIVIDE(50),
+       .CLKOUT0_DIVIDE((frequency == 32) ? 50 : 100),
        .DIVCLK_DIVIDE(1),
        .STARTUP_WAIT("FALSE"))
    PLLE2_BASE_inst