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updated for putting mdu on soc level

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This commit is contained in:
zeeshanrafique23 2021-08-14 22:15:32 +05:00
parent f15830e309
commit e630e5d2fd
9 changed files with 143 additions and 64 deletions
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2
mdu/mdu.core
View file

@ -23,7 +23,7 @@ targets:
mode : lint-only
verilator_options:
- "-Wall"
toplevel : serv_rf_top
toplevel : mdu_top
parameters:
WIDTH:

11
rtl/serv_bufreg.v
View file

@ -1,5 +1,6 @@
module serv_bufreg
(
module serv_bufreg #(
parameter MDU = 0
)(
input wire i_clk,
//State
input wire i_cnt0,
@ -44,6 +45,10 @@ module serv_bufreg
assign o_q = lsb[0] & i_en;
assign o_dbus_adr = {data, 2'b00};
assign o_mdu_rs1 = {o_dbus_adr[31:2],lsb};
assign o_lsb = i_mdu_en ? 2'b00 : lsb;
generate
if (MDU) assign o_lsb = i_mdu_en ? 2'b00 : lsb;
else assign o_lsb = lsb;
endgenerate
endmodule

44
rtl/serv_decode.v
View file

@ -1,7 +1,8 @@
`default_nettype none
module serv_decode #(
parameter [0:0] PRE_REGISTER = 1
)(
module serv_decode
#(parameter [0:0] PRE_REGISTER = 1,
parameter MDU = 0)
(
input wire clk,
//Input
input wire [31:2] i_wb_rdt,
@ -66,9 +67,30 @@ module serv_decode #(
reg imm25;
reg imm30;
//mdu
wire co_mdu_op = ((opcode == 5'b01100) & imm25);
wire [2:0]co_mdu_opcode = funct3;
generate
wire co_mdu_op;
wire [2:0]co_mdu_opcode;
wire co_shift_op;
wire co_slt_op;
wire co_mem_word;
wire co_rd_alu_en;
if (MDU) begin
assign co_mdu_op = ((opcode == 5'b01100) & imm25);
assign co_mdu_opcode = funct3;
assign co_shift_op = op_or_opimm & (funct3[1:0] == 2'b01) & !co_mdu_op;
assign co_slt_op = op_or_opimm & (funct3[2:1] == 2'b01) & !co_mdu_op;
assign co_mem_word = co_mdu_op ? co_mdu_op :funct3[1];
assign co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4] & !co_mdu_op;
end else begin
assign co_mdu_op = 1'b0;
assign co_mdu_opcode = 3'b0;
assign co_shift_op = op_or_opimm & (funct3[1:0] == 2'b01);
assign co_slt_op = op_or_opimm & (funct3[2:1] == 2'b01);
assign co_mem_word = funct3[1];
assign co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4];
end
endgenerate
//opcode
wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]);
@ -116,13 +138,6 @@ module serv_decode #(
wire co_sh_right = funct3[2];
wire co_bne_or_bge = funct3[0];
//
// opcode & funct3
//
wire co_shift_op = op_or_opimm & (funct3[1:0] == 2'b01) & !co_mdu_op;
wire co_slt_op = op_or_opimm & (funct3[2:1] == 2'b01) & !co_mdu_op;
//Matches system ops except eceall/ebreak/mret
wire csr_op = opcode[4] & opcode[2] & (|funct3);
@ -197,7 +212,6 @@ module serv_decode #(
wire co_mem_cmd = opcode[3];
wire co_mem_signed = ~funct3[2];
wire co_mem_word = co_mdu_op ? co_mdu_op :funct3[1];
wire co_mem_half = funct3[0];
wire [1:0] co_alu_bool_op = funct3[1:0];
@ -227,8 +241,6 @@ module serv_decode #(
//1 (OP_B_SOURCE_RS2) when BRANCH or OP
wire co_op_b_source = opcode[3];
wire co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4] & !co_mdu_op;
generate
if (PRE_REGISTER) begin

15
rtl/serv_mem_if.v
View file

@ -1,6 +1,7 @@
`default_nettype none
module serv_mem_if
#(parameter WITH_CSR = 1)
#(parameter WITH_CSR = 1,
parameter MDU = 0)
(
input wire i_clk,
//State
@ -60,8 +61,16 @@ module serv_mem_if
(i_half & !i_bytecnt[1]);
wire mem_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed);
wire mdu_rd = i_mdu_op & (dat_valid ? dat_cur : signbit & i_signed);
assign o_rd = mem_rd | mdu_rd;
generate
if(MDU) begin
wire mdu_rd = i_mdu_op & (dat_valid ? dat_cur : signbit & i_signed);
assign o_rd = mem_rd | mdu_rd;
end else begin
wire mdu_rd = 1'b0;
assign o_rd = mem_rd;
end
endgenerate
assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]);
assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word;

70
rtl/serv_rf_top.v
View file

@ -2,7 +2,11 @@
module serv_rf_top
#(parameter RESET_PC = 32'd0,
/* Multiplication and Division Unit
0 : Less hardware. Slow execution of multipy/devide instructions
1 : Increase hardware. Fast execution of multipy/devide instructions
*/
parameter MDU = 0,
/* Register signals before or after the decoder
0 : Register after the decoder. Faster but uses more resources
1 : (default) Register before the decoder. Slower but uses less resources
@ -55,8 +59,16 @@ module serv_rf_top
output wire o_dbus_we ,
output wire o_dbus_cyc,
input wire [31:0] i_dbus_rdt,
input wire i_dbus_ack);
input wire i_dbus_ack,
// MDU
output wire [31:0] ext_mdu_rs1,
output wire [31:0] ext_mdu_rs2,
output wire [ 2:0] ext_mdu_op,
output wire ext_mdu_valid,
input wire [31:0] ext_mdu_rd,
input wire ext_mdu_ready);
localparam CSR_REGS = WITH_CSR*4;
wire rf_wreq;
@ -79,13 +91,8 @@ module serv_rf_top
wire [RF_L2D-1:0] raddr;
wire [RF_WIDTH-1:0] rdata;
`ifdef MDU
wire [2:0] mdu_op;
wire mdu_valid;
wire mdu_ready;
wire [31:0] mdu_rs1;
wire [31:0] mdu_rd;
`endif
wire [31:0] dbus_rdt;
wire dbus_ack;
serv_rf_ram_if
#(.width (RF_WIDTH),
@ -124,23 +131,12 @@ module serv_rf_top
.i_raddr (raddr),
.o_rdata (rdata));
`ifdef MDU
mdu_top mdu_serv
(.i_clk(clk),
.i_rst(i_rst),
.i_mdu_rs1(mdu_rs1),
.i_mdu_rs2(o_dbus_dat),
.i_mdu_op(mdu_op),
.i_mdu_valid(mdu_valid),
.o_mdu_ready(mdu_ready),
.o_mdu_rd(mdu_rd));
`endif
serv_top
#(.RESET_PC (RESET_PC),
.PRE_REGISTER (PRE_REGISTER),
.RESET_STRATEGY (RESET_STRATEGY),
.WITH_CSR (WITH_CSR))
.WITH_CSR (WITH_CSR),
.MDU(MDU))
cpu
(
.clk (clk),
@ -187,19 +183,31 @@ module serv_rf_top
.o_ibus_cyc (o_ibus_cyc),
.i_ibus_rdt (i_ibus_rdt),
.i_ibus_ack (i_ibus_ack),
`ifdef MDU
.o_mdu_opcode (mdu_op),
.o_mdu_valid (mdu_valid),
.i_mdu_ready (mdu_ready),
`endif
// MDU
.o_mdu_opcode (ext_mdu_op),
.o_mdu_valid (ext_mdu_valid),
.i_mdu_ready (ext_mdu_ready),
.o_dbus_adr (o_dbus_adr),
.o_dbus_dat (o_dbus_dat),
.o_dbus_sel (o_dbus_sel),
.o_dbus_we (o_dbus_we),
.o_dbus_cyc (o_dbus_cyc),
.i_dbus_rdt (mdu_ready ? mdu_rd:i_dbus_rdt),
.i_dbus_ack (i_dbus_ack | mdu_ready),
.o_mdu_rs1 (mdu_rs1));
.i_dbus_rdt (dbus_rdt),
.i_dbus_ack (dbus_ack),
.o_mdu_rs1 (ext_mdu_rs1));
generate
if (MDU) begin
assign dbus_rdt = ext_mdu_ready ? ext_mdu_rd:i_dbus_rdt;
assign dbus_ack = i_dbus_ack | ext_mdu_ready;
end else begin
assign dbus_rdt = 32'b0;
assign dbus_ack = 1'b0;
end
assign ext_mdu_rs2 = o_dbus_dat;
endgenerate
endmodule
`default_nettype wire

18
rtl/serv_top.v
View file

@ -4,7 +4,8 @@ module serv_top
#(parameter WITH_CSR = 1,
parameter PRE_REGISTER = 1,
parameter RESET_STRATEGY = "MINI",
parameter RESET_PC = 32'd0)
parameter RESET_PC = 32'd0,
parameter MDU = 1'b0)
(
input wire clk,
input wire i_rst,
@ -46,11 +47,11 @@ module serv_top
output wire [4+WITH_CSR:0] o_rreg1,
input wire i_rdata0,
input wire i_rdata1,
`ifdef MDU
// MDU
output reg [ 2:0] o_mdu_opcode,
output reg o_mdu_valid,
input wire i_mdu_ready,
`endif
output wire [31:0] o_ibus_adr,
output wire o_ibus_cyc,
input wire [31:0] i_ibus_rdt,
@ -215,7 +216,8 @@ module serv_top
.o_rf_rd_en (rd_en));
serv_decode
#(.PRE_REGISTER (PRE_REGISTER))
#(.PRE_REGISTER (PRE_REGISTER),
.MDU(MDU))
decode
(
.clk (clk),
@ -293,7 +295,9 @@ module serv_top
.i_wb_en (i_ibus_ack),
.i_wb_rdt (i_ibus_rdt[31:7]));
serv_bufreg bufreg
serv_bufreg
#(.MDU(MDU))
bufreg
(
.i_clk (clk),
//State
@ -411,7 +415,8 @@ module serv_top
.o_csr (rf_csr_out));
serv_mem_if
#(.WITH_CSR (WITH_CSR))
#(.WITH_CSR (WITH_CSR),
.MDU(MDU))
mem_if
(
.i_clk (clk),
@ -536,7 +541,6 @@ module serv_top
rvfi_pc_wdata <= o_ibus_adr;
/* verilator lint_on COMBDLY */
`endif
endmodule

6
serv.core
View file

@ -25,6 +25,7 @@ targets:
default:
filesets : [core]
parameters :
- "is_toplevel? (MDU)"
- "is_toplevel? (PRE_REGISTER)"
- "is_toplevel? (RESET_STRATEGY)"
- RISCV_FORMAL
@ -43,6 +44,11 @@ targets:
toplevel : serv_rf_top
parameters:
MDU:
datatype : int
description: Enables RISC-V standard M-extension
paramtype : vlogparam
PRE_REGISTER:
datatype : int
description : Register signals before or after the decoder

2
servant.core
View file

@ -419,7 +419,7 @@ parameters:
MDU:
datatype : bool
paramtype : vlogdefine
paramtype : vlogparam
SERV_CLEAR_RAM:
datatype : bool

39
servant/servant.v
View file

@ -10,6 +10,7 @@ module servant
parameter reset_strategy = "MINI";
parameter sim = 0;
parameter with_csr = 1;
parameter MDU = 1;
wire timer_irq;
@ -52,6 +53,13 @@ module servant
wire wb_timer_cyc;
wire [31:0] wb_timer_rdt;
wire [31:0] mdu_rs1;
wire [31:0] mdu_rs2;
wire [ 2:0] mdu_op;
wire mdu_valid;
wire [31:0] mdu_rd;
wire mdu_ready;
servant_arbiter arbiter
(.i_wb_cpu_dbus_adr (wb_dmem_adr),
.i_wb_cpu_dbus_dat (wb_dmem_dat),
@ -149,7 +157,8 @@ module servant
serv_rf_top
#(.RESET_PC (32'h0000_0000),
.RESET_STRATEGY (reset_strategy),
.WITH_CSR (with_csr))
.WITH_CSR (with_csr),
.MDU(MDU))
cpu
(
.clk (wb_clk),
@ -190,6 +199,32 @@ module servant
.o_dbus_we (wb_dbus_we),
.o_dbus_cyc (wb_dbus_cyc),
.i_dbus_rdt (wb_dbus_rdt),
.i_dbus_ack (wb_dbus_ack));
.i_dbus_ack (wb_dbus_ack),
// MDU
.ext_mdu_rs1 (mdu_rs1),
.ext_mdu_rs2 (mdu_rs2),
.ext_mdu_op (mdu_op),
.ext_mdu_valid (mdu_valid),
.ext_mdu_rd (mdu_rd),
.ext_mdu_ready (mdu_ready));
generate
if(MDU) begin
mdu_top mdu_serv
(
.i_clk(wb_clk),
.i_rst(wb_rst),
.i_mdu_rs1(mdu_rs1),
.i_mdu_rs2(mdu_rs2),
.i_mdu_op(mdu_op),
.i_mdu_valid(mdu_valid),
.o_mdu_ready(mdu_ready),
.o_mdu_rd(mdu_rd));
end else begin
assign mdu_ready = 1'b0;
assign mdu_rd = 32'b0;
end
endgenerate
endmodule