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Move op_b mux to alu
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3 changed files with 14 additions and 16 deletions
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@ -5,7 +5,9 @@ module serv_alu
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input wire i_rst,
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input wire i_en,
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input wire i_rs1,
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input wire i_op_b,
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input wire i_rs2,
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input wire i_imm,
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input wire i_op_b_rs2,
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input wire i_buf,
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input wire i_init,
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input wire i_cnt_done,
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@ -38,7 +40,8 @@ module serv_alu
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wire plus_1;
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wire b_inv_plus_1;
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assign shamt_ser = i_sh_right ? i_op_b : b_inv_plus_1;
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wire op_b = i_op_b_rs2 ? i_rs2 : i_imm;
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assign shamt_ser = i_sh_right ? op_b : b_inv_plus_1;
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shift_reg #(.LEN (5)) shamt_reg
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(.clk (clk),
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@ -70,13 +73,13 @@ module serv_alu
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(
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.clk (clk),
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.rst (i_rst),
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.a (~i_op_b),
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.a (~op_b),
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.b (plus_1),
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.clr (!i_en),
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.q (b_inv_plus_1),
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.o_v (b_inv_plus_1_cy));
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wire add_b = i_sub ? b_inv_plus_1 : i_op_b;
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wire add_b = i_sub ? b_inv_plus_1 : op_b;
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ser_add ser_add
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(
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@ -92,7 +95,7 @@ module serv_alu
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(
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.i_clk (clk),
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.i_a (i_rs1),
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.i_b (i_op_b),
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.i_b (op_b),
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.i_clr (!i_en),
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.i_sign (i_cnt_done & !i_cmp_uns),
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.o_q (result_lt));
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@ -101,7 +104,7 @@ module serv_alu
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assign o_cmp = i_cmp_eq ? result_eq : result_lt;
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localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor
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wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, i_op_b}];
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wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, op_b}];
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assign o_rd = (i_rd_sel == ALU_RESULT_ADD) ? result_add :
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(i_rd_sel == ALU_RESULT_SR) ? result_sh :
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@ -119,6 +122,6 @@ module serv_alu
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en_r <= i_en;
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end
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assign result_eq = eq_r & (i_rs1 == i_op_b);
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assign result_eq = eq_r & (i_rs1 == op_b);
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endmodule
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@ -1,7 +1,3 @@
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localparam [0:0]
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OP_B_SOURCE_IMM = 1'd0,
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OP_B_SOURCE_RS2 = 1'd1;
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localparam[1:0]
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ALU_RESULT_ADD = 2'd0,
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ALU_RESULT_SR = 2'd1,
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@ -55,8 +55,6 @@ module serv_top
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input wire [31:0] i_dbus_rdt,
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input wire i_dbus_ack);
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`include "serv_params.vh"
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wire [4:0] rd_addr;
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wire [4:0] rs1_addr;
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wire [4:0] rs2_addr;
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@ -212,6 +210,7 @@ module serv_top
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.o_ctrl_pc_rel (pc_rel),
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.o_ctrl_mret (mret),
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//To alu
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.o_op_b_source (op_b_source),
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.o_alu_sub (alu_sub),
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.o_alu_bool_op (alu_bool_op),
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.o_alu_cmp_eq (alu_cmp_eq),
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@ -239,7 +238,6 @@ module serv_top
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.o_csr_d_sel (csr_d_sel),
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//To top
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.o_imm (imm),
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.o_op_b_source (op_b_source),
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.o_rd_csr_en (rd_csr_en),
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.o_rd_alu_en (rd_alu_en));
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@ -291,7 +289,6 @@ module serv_top
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.o_ibus_cyc (o_ibus_cyc),
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.i_ibus_ack (i_ibus_ack));
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assign op_b = (op_b_source == OP_B_SOURCE_IMM) ? imm : rs2;
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serv_alu alu
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(
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@ -299,7 +296,9 @@ module serv_top
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.i_rst (i_rst),
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.i_en (cnt_en),
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.i_rs1 (rs1),
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.i_op_b (op_b),
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.i_rs2 (rs2),
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.i_imm (imm),
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.i_op_b_rs2 (op_b_source),
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.i_buf (bufreg_q),
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.i_init (init),
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.i_cnt_done (cnt_done),
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