mirror of
https://github.com/olofk/serv.git
synced 2025-04-23 05:17:06 -04:00
Add vcd_start parameter
This commit is contained in:
parent
40e7855bac
commit
ed02951b4d
2 changed files with 24 additions and 2 deletions
|
@ -117,12 +117,21 @@ int main(int argc, char **argv, char **env)
|
|||
if (arg_timeout[0])
|
||||
timeout = atoi(arg_timeout+9);
|
||||
|
||||
vluint64_t vcd_start = 0;
|
||||
const char *arg_vcd_start = Verilated::commandArgsPlusMatch("vcd_start=");
|
||||
if (arg_vcd_start[0])
|
||||
vcd_start = atoi(arg_vcd_start+11);
|
||||
|
||||
bool dump = false;
|
||||
top->wb_clk = 1;
|
||||
bool q = top->q;
|
||||
while (!(done || Verilated::gotFinish())) {
|
||||
if (tfp && !dump && (main_time > vcd_start)) {
|
||||
dump = true;
|
||||
}
|
||||
top->wb_rst = main_time < 100;
|
||||
top->eval();
|
||||
if (tfp)
|
||||
if (dump)
|
||||
tfp->dump(main_time);
|
||||
if (baud_rate)
|
||||
do_uart(&uart_context, top->q);
|
||||
|
|
15
servant.core
15
servant.core
|
@ -102,7 +102,15 @@ targets:
|
|||
verilator_tb:
|
||||
default_tool: verilator
|
||||
filesets : [soc, verilator_tb]
|
||||
parameters : [RISCV_FORMAL, firmware, memsize, signature, timeout, uart_baudrate, vcd]
|
||||
parameters :
|
||||
- RISCV_FORMAL
|
||||
- firmware
|
||||
- memsize
|
||||
- signature
|
||||
- timeout
|
||||
- uart_baudrate
|
||||
- vcd
|
||||
- vcd_start
|
||||
tools:
|
||||
verilator:
|
||||
verilator_options : [--trace]
|
||||
|
@ -155,6 +163,11 @@ parameters:
|
|||
datatype : bool
|
||||
paramtype : plusarg
|
||||
|
||||
vcd_start:
|
||||
datatype : int
|
||||
description : Delay start of VCD dumping until the specified time
|
||||
paramtype : plusarg
|
||||
|
||||
generate:
|
||||
icebreaker_pll:
|
||||
generator: icepll
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue