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Add explicit wire defs to ports

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This commit is contained in:
Olof Kindgren 2018-11-17 21:30:03 +01:00
parent 0036756157
commit f66f82a57a
16 changed files with 251 additions and 248 deletions
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4
bench/serv_wrapper.v
View file

@ -1,8 +1,8 @@
`default_nettype none
module serv_wrapper
(
input wb_clk,
input wb_rst);
input wire wb_clk,
input wire wb_rst);
parameter firmware = "firmware.hex";

20
rtl/riscv_timer.v
View file

@ -1,18 +1,18 @@
`default_nettype none
module riscv_timer
(input i_clk,
(input wire i_clk,
output reg o_irq = 1'b0,
input [31:0] i_wb_adr,
input [31:0] i_wb_dat,
input [3:0] i_wb_sel,
input i_wb_we,
input i_wb_cyc,
input i_wb_stb,
input wire [31:0] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output reg [31:0] o_wb_dat,
output reg o_wb_ack = 1'b0);
reg [63:0] mtime = 64'd0;
reg [63:0] mtimecmp = 64'd0;
reg [63:0] mtime = 64'd0;
reg [63:0] mtimecmp = 64'd0;
localparam [1:0]
REG_MTIMELO = 2'd0,
@ -20,7 +20,7 @@ module riscv_timer
REG_MTIMECMPLO = 2'd2,
REG_MTIMECMPHI = 2'd3;
always @(i_wb_adr)
always @(i_wb_adr, mtime, mtimecmp)
case (i_wb_adr[3:2])
REG_MTIMELO : o_wb_dat = mtime[31:0];
REG_MTIMEHI : o_wb_dat = mtime[63:32];

19
rtl/ser_add.v
View file

@ -1,16 +1,17 @@
`default_nettype none
module ser_add
(
input clk,
input a,
input b,
input clr,
output q,
output o_v);
input wire clk,
input wire a,
input wire b,
input wire clr,
output wire q,
output wire o_v);
reg c_r = 1'b0;
assign o_v = (a&b | a&c_r | b&c_r);
reg c_r = 1'b0;
assign q = a ^ b ^ c_r;
always @(posedge clk)
c_r <= !clr & o_v;

10
rtl/ser_eq.v
View file

@ -1,14 +1,14 @@
`default_nettype none
module ser_eq
(
input clk,
input a,
input b,
input clr,
input wire clk,
input wire a,
input wire b,
input wire clr,
output reg o_q);
reg eq = 1'b1;
wire q = eq & (a == b);
always @(posedge clk) begin
eq <= q | clr;

8
rtl/ser_lt.v
View file

@ -1,10 +1,10 @@
`default_nettype none
module ser_lt
(
input i_clk,
input i_a,
input i_b,
input i_clr,
input wire i_clk,
input wire i_a,
input wire i_b,
input wire i_clr,
output reg o_q);
reg lt_r = 1'b0;

31
rtl/ser_shift.v
View file

@ -1,20 +1,20 @@
`default_nettype none
module ser_shift
(
input i_clk,
input i_load,
input [4:0] i_shamt,
input i_signed,
input i_right,
input i_d,
output o_q);
input wire i_clk,
input wire i_load,
input wire [4:0] i_shamt,
input wire i_signed,
input wire i_right,
input wire i_d,
output wire o_q);
wire [31:0] shiftreg;
wire [31:0] shiftreg;
reg signbit = 1'b0;
reg wrapped = 1'b0;
reg [4:0] cnt = 5'd0;
reg signbit = 1'b0;
reg wrapped = 1'b0;
reg [4:0] cnt = 5'd0;
shift_reg #(.LEN (32)) sh_reg
(.clk (i_clk),
.i_en (i_load),
@ -33,13 +33,10 @@ module ser_shift
wrapped <= 1'b0;
end
end
wire shiftreg_valid = (i_shamt == 0) | (wrapped^i_right);
assign o_q = shiftreg_valid ? shiftreg[cnt] : signbit & i_signed;
endmodule
endmodule

47
rtl/serv_alu.v
View file

@ -1,21 +1,21 @@
`default_nettype none
module serv_alu
(
input clk,
input i_en,
input i_rs1,
input i_op_b,
input i_init,
input i_sub,
input i_cmp_sel,
input i_cmp_neg,
input i_cmp_uns,
output o_cmp,
input i_shamt_en,
input i_sh_right,
input i_sh_signed,
input [2:0] i_rd_sel,
output o_rd);
input wire clk,
input wire i_en,
input wire i_rs1,
input wire i_op_b,
input wire i_init,
input wire i_sub,
input wire i_cmp_sel,
input wire i_cmp_neg,
input wire i_cmp_uns,
output wire o_cmp,
input wire i_shamt_en,
input wire i_sh_right,
input wire i_sh_signed,
input wire [2:0] i_rd_sel,
output wire o_rd);
`include "serv_params.vh"
@ -23,16 +23,16 @@ module serv_alu
wire result_eq;
wire result_lt;
wire result_sh;
wire [4:0] shamt;
reg en_r;
wire v;
reg msb_lt = 1'b0;
reg init_r;
wire shamt_l;
wire shamt_ser;
ser_add ser_add_inv_shamt_plus1
(
.clk (clk),
@ -74,7 +74,7 @@ module serv_alu
.o_v ());
wire add_b = i_sub ? b_inv_plus_1 : i_op_b;
ser_add ser_add
(
.clk (clk),
@ -101,9 +101,9 @@ module serv_alu
.o_q (result_lt));
reg last_eq;
wire result_lt2 = last_eq ? result_lt : msb_lt;
assign o_cmp = i_cmp_neg^((i_cmp_sel == ALU_CMP_EQ) ? result_eq : result_lt2);
assign o_rd = (i_rd_sel == ALU_RESULT_ADD) ? result_add :
@ -119,10 +119,9 @@ module serv_alu
last_eq <= i_rs1 == i_op_b;
msb_lt <= i_cmp_uns ? (~i_rs1 & i_op_b) : (i_rs1 & ~i_op_b);
end
en_r <= i_en;
init_r <= i_init;
end
endmodule

20
rtl/serv_csr.v
View file

@ -1,16 +1,16 @@
`default_nettype none
module serv_csr
(
input i_clk,
input i_en,
input [2:0] i_csr_sel,
input [1:0] i_csr_source,
input i_trap,
input i_pc,
input i_mtval,
input [3:0] i_mcause,
input i_d,
output o_q);
input wire i_clk,
input wire i_en,
input wire [2:0] i_csr_sel,
input wire [1:0] i_csr_source,
input wire i_trap,
input wire i_pc,
input wire i_mtval,
input wire [3:0] i_mcause,
input wire i_d,
output wire o_q);
`include "serv_params.vh"
/*

34
rtl/serv_ctrl.v
View file

@ -1,23 +1,23 @@
`default_nettype none
module serv_ctrl
(
input clk,
input i_en,
input i_pc_en,
input i_cnt_done,
input i_jump,
input i_offset,
input i_rs1,
input i_jalr,
input i_auipc,
input i_trap,
input i_csr_pc,
output o_rd,
output o_bad_pc,
output reg o_misalign = 1'b0,
output [31:0] o_ibus_adr,
output reg o_ibus_cyc = 1'b0,
input i_ibus_ack);
input wire clk,
input wire i_en,
input wire i_pc_en,
input wire i_cnt_done,
input wire i_jump,
input wire i_offset,
input wire i_rs1,
input wire i_jalr,
input wire i_auipc,
input wire i_trap,
input wire i_csr_pc,
output wire o_rd,
output wire o_bad_pc,
output reg o_misalign = 1'b0,
output wire [31:0] o_ibus_adr,
output reg o_ibus_cyc = 1'b0,
input wire i_ibus_ack);
parameter RESET_PC = 32'd8;

113
rtl/serv_decode.v
View file

@ -1,52 +1,52 @@
`default_nettype none
module serv_decode
(
input clk,
input [31:0] i_wb_rdt,
input i_wb_en,
output o_cnt_done,
output o_ibus_active,
output o_ctrl_en,
output o_ctrl_pc_en,
output o_ctrl_jump,
output o_ctrl_jalr,
output o_ctrl_auipc,
output o_ctrl_trap,
output o_ctrl_mret,
input i_ctrl_misalign,
output o_rf_rd_en,
output reg [4:0] o_rf_rd_addr,
output o_rf_rs_en,
output reg [4:0] o_rf_rs1_addr,
output reg [4:0] o_rf_rs2_addr,
output o_alu_en,
output o_alu_init,
output o_alu_sub,
output reg o_alu_cmp_sel,
output o_alu_cmp_neg,
output reg o_alu_cmp_uns,
input i_alu_cmp,
output o_alu_shamt_en,
output o_alu_sh_signed,
output o_alu_sh_right,
output reg [2:0] o_alu_rd_sel,
output o_mem_en,
output o_mem_cmd,
output o_mem_init,
output reg o_mem_dat_valid,
input i_mem_dbus_ack,
input i_mem_misalign,
output o_csr_en,
output reg [2:0] o_csr_sel,
output reg [1:0] o_csr_source,
output reg [3:0] o_csr_mcause,
output o_csr_imm,
output o_csr_d_sel,
output reg [2:0] o_funct3,
output reg o_imm,
output o_offset_source,
output o_op_b_source,
output [2:0] o_rd_source);
input wire clk,
input wire [31:0] i_wb_rdt,
input wire i_wb_en,
output wire o_cnt_done,
output wire o_ibus_active,
output wire o_ctrl_en,
output wire o_ctrl_pc_en,
output wire o_ctrl_jump,
output wire o_ctrl_jalr,
output wire o_ctrl_auipc,
output wire o_ctrl_trap,
output wire o_ctrl_mret,
input wire i_ctrl_misalign,
output wire o_rf_rd_en,
output reg [4:0] o_rf_rd_addr,
output wire o_rf_rs_en,
output reg [4:0] o_rf_rs1_addr,
output reg [4:0] o_rf_rs2_addr,
output wire o_alu_en,
output wire o_alu_init,
output wire o_alu_sub,
output reg o_alu_cmp_sel,
output wire o_alu_cmp_neg,
output reg o_alu_cmp_uns,
input wire i_alu_cmp,
output wire o_alu_shamt_en,
output wire o_alu_sh_signed,
output wire o_alu_sh_right,
output reg [2:0] o_alu_rd_sel,
output wire o_mem_en,
output wire o_mem_cmd,
output wire o_mem_init,
output reg o_mem_dat_valid,
input wire i_mem_dbus_ack,
input wire i_mem_misalign,
output wire o_csr_en,
output reg [2:0] o_csr_sel,
output reg [1:0] o_csr_source,
output reg [3:0] o_csr_mcause,
output wire o_csr_imm,
output wire o_csr_d_sel,
output reg [2:0] o_funct3,
output reg o_imm,
output wire o_offset_source,
output wire o_op_b_source,
output wire [2:0] o_rd_source);
`include "serv_params.vh"
@ -68,7 +68,7 @@ module serv_decode
OP_JAL = 5'b11011,
OP_SYSTEM = 5'b11100;
reg [2:0] state = IDLE;
reg [1:0] state = IDLE;
reg [4:0] cnt = 5'd0;
@ -180,10 +180,10 @@ module serv_decode
//12'hf14 : o_csr_sel = CSR_SEL_MHARTID;
default : begin
o_csr_sel = 3'bxxx;
if (o_csr_en) begin
/*if (o_csr_en) begin
$display("%0t: CSR %03h not implemented", $time, imm[31:20]);
//#100 $finish;
end
end*/
end
endcase
if (o_ctrl_trap)
@ -192,7 +192,7 @@ module serv_decode
o_csr_sel = CSR_SEL_MEPC;
end
assign o_csr_imm = (cnt < 5) ? o_rf_rs1_addr[cnt] : 1'b0;
assign o_csr_imm = (cnt < 5) ? o_rf_rs1_addr[cnt[2:0]] : 1'b0;
assign o_csr_d_sel = o_funct3[2];
assign o_alu_shamt_en = (cnt < 5) & (state == INIT);
@ -296,16 +296,15 @@ module serv_decode
assign o_ctrl_trap = (state == TRAP);
always @(i_mem_misalign, o_mem_cmd, e_op, imm) begin
o_csr_mcause[3:0] <= 4'd0;
o_csr_mcause[3:0] = 4'd0;
if (i_mem_misalign & !o_mem_cmd)
o_csr_mcause[3:0] <= 4'd4;
o_csr_mcause[3:0] = 4'd4;
if (i_mem_misalign & o_mem_cmd)
o_csr_mcause[3:0] <= 4'd6;
o_csr_mcause[3:0] = 4'd6;
if (e_op & !imm[20])
o_csr_mcause[3:0] <= 4'd11;
o_csr_mcause[3:0] = 4'd11;
if (e_op & imm[20])
o_csr_mcause[3:0] <= 4'd3;
//if (o_ctrl_jump & i_ctrl_misalign)
o_csr_mcause[3:0] = 4'd3;
end
always @(posedge clk) begin
@ -343,7 +342,7 @@ module serv_decode
cnt <= cnt + {4'd0,cnt_en};
end
`define SERV_DECODE_CHECKS
//`define SERV_DECODE_CHECKS
`ifdef SERV_DECODE_CHECKS
reg unknown_op = 1'b0;

40
rtl/serv_mem_if.v
View file

@ -1,27 +1,27 @@
`default_nettype none
module serv_mem_if
(
input i_clk,
input i_en,
input i_init,
input i_dat_valid,
input i_cmd,
input [2:0] i_funct3,
input i_rs1,
input i_rs2,
input i_imm,
output o_rd,
output o_misalign,
input i_trap,
input wire i_clk,
input wire i_en,
input wire i_init,
input wire i_dat_valid,
input wire i_cmd,
input wire [2:0] i_funct3,
input wire i_rs1,
input wire i_rs2,
input wire i_imm,
output wire o_rd,
output wire o_misalign,
input wire i_trap,
//External interface
output [31:0] o_wb_adr,
output reg [31:0] o_wb_dat = 32'd0,
output [3:0] o_wb_sel,
output o_wb_we ,
output reg o_wb_cyc = 1'b0,
output o_wb_stb,
input [31:0] i_wb_rdt,
input i_wb_ack);
output wire [31:0] o_wb_adr,
output reg [31:0] o_wb_dat = 32'd0,
output wire [3:0] o_wb_sel,
output wire o_wb_we ,
output reg o_wb_cyc = 1'b0,
output wire o_wb_stb,
input wire [31:0] i_wb_rdt,
input wire i_wb_ack);
wire wb_en = o_wb_cyc & i_wb_ack;
assign o_wb_stb = o_wb_cyc;

32
rtl/serv_regfile.v
View file

@ -1,15 +1,15 @@
`default_nettype none
module serv_regfile
(
input i_clk,
input i_rd_en,
input [4:0] i_rd_addr,
input i_rd,
input [4:0] i_rs1_addr,
input [4:0] i_rs2_addr,
input i_rs_en,
output o_rs1,
output o_rs2);
input wire i_clk,
input wire i_rd_en,
input wire [4:0] i_rd_addr,
input wire i_rd,
input wire [4:0] i_rs1_addr,
input wire [4:0] i_rs2_addr,
input wire i_rs_en,
output wire o_rs1,
output wire o_rs2);
//reg [31:0] rf [0:31];
@ -48,7 +48,7 @@ module serv_regfile
dbg_x30[i] = rf[i][30];
dbg_x31[i] = rf[i][31];
end
*/
*/
reg [31:0] dbg_x0 ;
reg [31:0] dbg_x1 ;
reg [31:0] dbg_x2 ;
@ -81,21 +81,21 @@ module serv_regfile
reg [31:0] dbg_x29;
reg [31:0] dbg_x30;
reg [31:0] dbg_x31;
integer i;
// initial for (i=0; i<32; i=i+1) rf[i] = 0;
`endif
reg [4:0] raddr = 5'd1;
reg [4:0] waddr = 5'd0;
// reg [31:0] rs = 32'd0;
wire [31:0] rs;
reg [31:0] mask;
always @(i_rd_addr)
mask = ~(1 << i_rd_addr);
SB_RAM40_4K rf0
(
.RDATA (rs[15:0]),
@ -136,8 +136,8 @@ module serv_regfile
//rs <= rf[raddr2];
end
wire [4:0] raddr2 = raddr & {5{i_rs_en}};
assign o_rs1 = (|i_rs1_addr) ? rs[i_rs1_addr] : 1'b0;
assign o_rs2 = (|i_rs2_addr) ? rs[i_rs2_addr] : 1'b0;
endmodule

68
rtl/serv_top.v
View file

@ -8,42 +8,42 @@
module serv_top
(
input clk,
input wire clk,
`ifdef RISCV_FORMAL
output reg rvfi_valid = 1'b0,
output reg [63:0] rvfi_order = 64'd0,
output reg [31:0] rvfi_insn = 32'd0,
output reg rvfi_trap = 1'b0,
output reg rvfi_halt = 1'b0,
output reg rvfi_intr = 1'b0,
output reg [1:0] rvfi_mode = 2'b11,
output reg [4:0] rvfi_rs1_addr,
output reg [4:0] rvfi_rs2_addr,
output reg [31:0] rvfi_rs1_rdata,
output reg [31:0] rvfi_rs2_rdata,
output reg [4:0] rvfi_rd_addr,
output reg [31:0] rvfi_rd_wdata,
output reg [31:0] rvfi_pc_rdata,
output reg [31:0] rvfi_pc_wdata,
output reg [31:0] rvfi_mem_addr,
output reg [3:0] rvfi_mem_rmask,
output reg [3:0] rvfi_mem_wmask,
output reg [31:0] rvfi_mem_rdata,
output reg [31:0] rvfi_mem_wdata,
output reg rvfi_valid = 1'b0,
output reg [63:0] rvfi_order = 64'd0,
output reg [31:0] rvfi_insn = 32'd0,
output reg rvfi_trap = 1'b0,
output reg rvfi_halt = 1'b0,
output reg rvfi_intr = 1'b0,
output reg [1:0] rvfi_mode = 2'b11,
output reg [4:0] rvfi_rs1_addr,
output reg [4:0] rvfi_rs2_addr,
output reg [31:0] rvfi_rs1_rdata,
output reg [31:0] rvfi_rs2_rdata,
output reg [4:0] rvfi_rd_addr,
output reg [31:0] rvfi_rd_wdata,
output reg [31:0] rvfi_pc_rdata,
output reg [31:0] rvfi_pc_wdata,
output reg [31:0] rvfi_mem_addr,
output reg [3:0] rvfi_mem_rmask,
output reg [3:0] rvfi_mem_wmask,
output reg [31:0] rvfi_mem_rdata,
output reg [31:0] rvfi_mem_wdata,
`endif
output [31:0] o_ibus_adr,
output o_ibus_cyc,
output o_ibus_stb,
input [31:0] i_ibus_rdt,
input i_ibus_ack,
output [31:0] o_dbus_adr,
output [31:0] o_dbus_dat,
output [3:0] o_dbus_sel,
output o_dbus_we ,
output o_dbus_cyc,
output o_dbus_stb,
input [31:0] i_dbus_rdt,
input i_dbus_ack);
output wire [31:0] o_ibus_adr,
output wire o_ibus_cyc,
output wire o_ibus_stb,
input wire [31:0] i_ibus_rdt,
input wire i_ibus_ack,
output wire [31:0] o_dbus_adr,
output wire [31:0] o_dbus_dat,
output wire [3:0] o_dbus_sel,
output wire o_dbus_we ,
output wire o_dbus_cyc,
output wire o_dbus_stb,
input wire [31:0] i_dbus_rdt,
input wire i_dbus_ack);
assign o_ibus_stb = o_ibus_cyc;

12
rtl/shift_reg.v
View file

@ -1,15 +1,15 @@
module shift_reg
(
input clk,
input i_en,
input i_d,
output o_q,
output [LEN-2:0] o_par);
input wire clk,
input wire i_en,
input wire i_d,
output wire o_q,
output wire [LEN-2:0] o_par);
parameter LEN = 0;
parameter INIT = 0;
reg [LEN-1:0] data = INIT;
reg [LEN-1:0] data = INIT;
assign o_q = data[0];
assign o_par = data[LEN-1:1];
always @(posedge clk)

15
testhalt.v
View file

@ -1,19 +1,20 @@
`default_nettype none
module testhalt
(
input i_wb_clk,
input [31:0] i_wb_dat,
input i_wb_we,
input i_wb_cyc,
input i_wb_stb,
output reg o_wb_ack = 1'b0);
input wire i_wb_clk,
input wire [31:0] i_wb_dat,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output reg o_wb_ack = 1'b0);
always @(posedge i_wb_clk) begin
`ifndef SYNTHESIS
if (i_wb_cyc & i_wb_stb) begin
$display("Test complete");
$finish;
end
`endif
if (i_wb_cyc & i_wb_stb & !o_wb_ack)
o_wb_ack <= 1'b1;
end

26
testprint.v
View file

@ -1,20 +1,21 @@
`default_nettype none
module testprint
(
input i_wb_clk,
input wire i_wb_clk,
input wire [31:0] i_wb_dat,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output reg o_wb_ack = 1'b0);
input [31:0] i_wb_dat,
input i_wb_we,
input i_wb_cyc,
input i_wb_stb,
output reg o_wb_ack /* verilator public */ = 1'b0);
wire wb_en;
wire wb_en /* verilator public */;
wire [7:0] ch /* verilator public */;
wire [7:0] ch;
assign ch = i_wb_dat[7:0];
assign wb_en = i_wb_cyc & i_wb_stb;
`ifndef SYNTHESIS
//synthesis translate_off
reg [1023:0] signature_file;
integer f = 0;
@ -23,9 +24,12 @@ module testprint
$display("Writing signature to %0s", signature_file);
f = $fopen(signature_file, "w");
end
//synthesis translate_on
`endif
always @(posedge i_wb_clk) begin
o_wb_ack <= 1'b0;
`ifndef SYNTHESIS
//synthesis translate_off
if (wb_en & o_wb_ack) begin
if (f)
$fwrite(f, "%c", i_wb_dat[7:0]);
@ -34,6 +38,8 @@ module testprint
$fflush();
`endif
end
//synthesis translate_on
`endif
if (wb_en & !o_wb_ack)
o_wb_ack <= 1'b1;
end