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support for W=4

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uhit332 2023-10-31 13:11:09 +01:00 • committed by Olof Kindgren
parent a8fbf688c5
commit f9d6b23543
1 changed files with 10 additions and 6 deletions
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16
rtl/serv_mem_if.v
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@ -1,6 +1,10 @@
`default_nettype none
module serv_mem_if
#(parameter [0:0] WITH_CSR = 1)
#(
parameter [0:0] WITH_CSR = 1,
parameter W = 1,
parameter B = W-1
)
(
input wire i_clk,
//State
@ -15,12 +19,12 @@ module serv_mem_if
//MDU
input wire i_mdu_op,
//Data
input wire i_bufreg2_q,
output wire o_rd,
input wire [B:0] i_bufreg2_q,
output wire [B:0] o_rd,
//External interface
output wire [3:0] o_wb_sel);
reg signbit;
reg signbit;
/*
Before a store operation, the data to be written needs to be shifted into
@ -43,7 +47,7 @@ module serv_mem_if
(i_bytecnt == 2'b00) |
(i_half & !i_bytecnt[1]);
assign o_rd = dat_valid ? i_bufreg2_q : signbit & i_signed;
assign o_rd = dat_valid ? i_bufreg2_q : {W{i_signed & signbit}};
assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]);
assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word;
@ -52,7 +56,7 @@ module serv_mem_if
always @(posedge i_clk) begin
if (dat_valid)
signbit <= i_bufreg2_q;
signbit <= i_bufreg2_q[B];
end
/*