Add icepll generator and run tinyfpga BX at 32MHz

README.md

@@ -75,7 +75,7 @@ Only supported so far is a single threaded Zephyr hello world example on the ice
 
 TinyFPGA BX
 
-Pin B3 is used for UART output with 57600 baud rate.
+Pin A6 is used for UART output with 115200 baud rate.
 
     cd $SERV/workspace
     fusesoc run --target=tinyfpga_bx serv

bench/serv_wrapper.v

@@ -1,19 +1,21 @@
 `default_nettype none
 module serv_wrapper
 (
- input wire  wb_clk,
+ input wire  i_clk,
  output wire q);
 
    parameter memfile = "zephyr_hello.hex";
    parameter memsize = 8192;
+   parameter PLL = "NONE";
 
+   wire      wb_clk;
+   wire      wb_rst;
 
-   reg [4:0] rst_reg = 5'b11111;
-
-   always @(posedge wb_clk)
-     rst_reg <= {1'b0, rst_reg[4:1]};
-
-   wire      wb_rst = rst_reg[0];
+   serv_clock_gen #(.PLL (PLL))
+   clock_gen
+     (.i_clk (i_clk),
+      .o_clk (wb_clk),
+      .o_rst (wb_rst));
 
    wire 	timer_irq;
 

data/icebreaker.pcf

@@ -1,5 +1,5 @@
 # 12 MHz clock
-set_io wb_clk        35
+set_io i_clk        35
 
 # RS232
 set_io q 9

data/tinyfpga_bx.pcf

@@ -1,2 +1,2 @@
-set_io q B3
-set_io wb_clk B2
+set_io q A6
+set_io i_clk B2

rtl/serv_clock_gen.v

@@ -0,0 +1,51 @@
+`default_nettype none
+module serv_clock_gen
+  (
+   input  i_clk,
+   output o_clk,
+   output o_rst);
+
+   parameter PLL = "NONE";
+
+   generate
+      if (PLL == "ICE40_CORE") begin
+	 wire locked;
+	 SB_PLL40_CORE
+	   #(`include "pll.vh")
+	 pll
+	   (
+	    .LOCK(locked),
+	    .RESETB(1'b1),
+	    .BYPASS(1'b0),
+	    .REFERENCECLK(i_clk),
+	    .PLLOUTCORE(o_clk));
+	 reg [1:0] rst_reg;
+	 always @(posedge o_clk)
+	   rst_reg <= {!locked, rst_reg[1]};
+	 assign o_rst = rst_reg[0];
+      end else if (PLL == "ICE40_PAD") begin
+	 wire locked;
+	 SB_PLL40_PAD
+	   #(`include "pll.vh")
+	 pll
+	   (
+	    .LOCK(locked),
+	    .RESETB(1'b1),
+	    .BYPASS(1'b0),
+	    .PACKAGEPIN (i_clk),
+	    .PLLOUTCORE(o_clk));
+	 reg [1:0] rst_reg;
+	 always @(posedge o_clk)
+	   rst_reg <= {!locked, rst_reg[1]};
+	 assign o_rst = rst_reg[0];
+      end else begin
+	 assign o_clk = i_clk;
+
+	 reg [4:0] rst_reg = 5'b11111;
+
+	 always @(posedge o_clk)
+	   rst_reg <= {1'b0, rst_reg[4:1]};
+	 assign o_rst = rst_reg[0];
+      end
+   endgenerate
+endmodule

serv.core

@@ -25,7 +25,7 @@ filesets:
       - sw/blinky.hex       : {copyto : blinky.hex}
       - sw/zephyr_hello.hex : {copyto : zephyr_hello.hex}
     file_type : user
-      
+
   serv_top_tb:
     files:
       - bench/serv_top_tb.v
@@ -34,13 +34,14 @@ filesets:
 
   wrapper:
     files:
+      - rtl/serv_clock_gen.v
       - rtl/riscv_timer.v
       - rtl/wb_gpio.v
       - bench/serv_arbiter.v
       - bench/serv_mux.v
       - bench/serv_wrapper.v
     file_type : verilogSource
-    depend : [wb_ram]
+    depend : [wb_ram, "fusesoc:utils:generators"]
 
   netlist:
     files: [synth.v : {file_type : verilogSource}]
@@ -65,10 +66,11 @@ targets:
   icebreaker:
     default_tool : icestorm
     filesets : [core, mem_files, wrapper, icebreaker]
-    parameters : [memfile, memsize]
+    generate: [icebreaker_pll]
+    parameters : [memfile, memsize, PLL=ICE40_PAD]
     tools:
       icestorm:
-        nextpnr_options: [--up5k, --freq, 12]
+        nextpnr_options: [--up5k, --freq, 16]
         pnr: next
     toplevel : serv_wrapper
 
@@ -80,10 +82,11 @@ targets:
   tinyfpga_bx:
     default_tool : icestorm
     filesets : [core, mem_files, wrapper, tinyfpga_bx]
-    parameters : [memfile, memsize]
+    generate: [tinyfpga_bx_pll]
+    parameters : [memfile, memsize, PLL=ICE40_CORE]
     tools:
       icestorm:
-        nextpnr_options : [--lp8k, --package, cm81, --freq, 16]
+        nextpnr_options : [--lp8k, --package, cm81, --freq, 32]
         pnr: next
     toplevel : serv_wrapper
 
@@ -116,6 +119,11 @@ targets:
     toplevel : serv_wrapper
 
 parameters:
+  PLL:
+    datatype : str
+    description : PLL type to use for main clock generation
+    paramtype : vlogparam
+
   RISCV_FORMAL:
     datatype  : bool
     paramtype : vlogdefine
@@ -147,3 +155,15 @@ parameters:
   vcd:
     datatype : bool
     paramtype : plusarg
+
+generate:
+  icebreaker_pll:
+    generator: icepll
+    parameters:
+      freq_out : 16
+
+  tinyfpga_bx_pll:
+    generator: icepll
+    parameters:
+      freq_in  : 16
+      freq_out : 32