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Add cmod-a7-35t target.

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Bruno Flores 2020-10-24 11:54:27 +00:00 • committed by Olof Kindgren
parent d7e9b39c13
commit fe90ff7f97
2 changed files with 29 additions and 0 deletions
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14
data/cmod_a7_35t.xdc Normal file
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@ -0,0 +1,14 @@
## 12 MHz Clock Signal
set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { i_clk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports { i_clk }];
## LEDs
set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { q }]; #IO_L12N_T1_MRCC_16 Sch=led[1]
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { q }]; #IO_L13P_T2_MRCC_16 Sch=led[2]
## UART
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { q }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { q }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

15
servant.core
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@ -72,6 +72,13 @@ filesets:
- servant/servix_clock_gen.v : {file_type : verilogSource}
- servant/servix.v : {file_type : verilogSource}
- data/nexys_a7.xdc : {file_type : xdc}
cmod_a7_35t:
files:
- servant/servix_clock_gen.v : {file_type : verilogSource}
- servant/servix.v : {file_type : verilogSource}
- data/cmod_a7_35t.xdc : {file_type : xdc}
arty_a7_35t:
files:
- servant/servix_clock_gen.v : {file_type : verilogSource}
@ -213,6 +220,14 @@ targets:
vivado: {part : xc7a100tcsg324-1}
toplevel : servix
cmod_a7_35t:
default_tool: vivado
filesets : [mem_files, soc, cmod_a7_35t]
parameters : [memfile=blinky.hex, memsize, frequency=12]
tools:
vivado: {part : xc7a35tcpg236-1}
toplevel : servix
arty_a7_35t:
default_tool: vivado
filesets : [mem_files, soc, arty_a7_35t]