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updated the mdu valid signal

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zeeshanrafique23 2021-07-13 18:04:34 +05:00
parent 45e0b4b98b
commit fea7b5208d
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rtl/serv_state.v
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@ -81,7 +81,7 @@ module serv_state
wire two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op | i_mdu_op;
//valid signal for mdu
assign o_mdu_valid = i_mdu_op & o_cnt_done;
assign o_mdu_valid = !o_cnt_en & init_done & i_mdu_op;
assign o_dbus_cyc = !o_cnt_en & init_done & i_mem_op & !i_mem_misalign;