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39 lines
1.3 KiB
Verilog
39 lines
1.3 KiB
Verilog
/* Arbitrates between dbus and ibus accesses.
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* Relies on the fact that not both masters are active at the same time
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*/
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module servant_arbiter
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(
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input wire [31:0] i_wb_cpu_dbus_adr,
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input wire [31:0] i_wb_cpu_dbus_dat,
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input wire [3:0] i_wb_cpu_dbus_sel,
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input wire i_wb_cpu_dbus_we,
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input wire i_wb_cpu_dbus_cyc,
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output wire [31:0] o_wb_cpu_dbus_rdt,
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output wire o_wb_cpu_dbus_ack,
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input wire [31:0] i_wb_cpu_ibus_adr,
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input wire i_wb_cpu_ibus_cyc,
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output wire [31:0] o_wb_cpu_ibus_rdt,
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output wire o_wb_cpu_ibus_ack,
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output wire [31:0] o_wb_cpu_adr,
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output wire [31:0] o_wb_cpu_dat,
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output wire [3:0] o_wb_cpu_sel,
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output wire o_wb_cpu_we,
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output wire o_wb_cpu_cyc,
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input wire [31:0] i_wb_cpu_rdt,
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input wire i_wb_cpu_ack);
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assign o_wb_cpu_dbus_rdt = i_wb_cpu_rdt;
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assign o_wb_cpu_dbus_ack = i_wb_cpu_ack & !i_wb_cpu_ibus_cyc;
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assign o_wb_cpu_ibus_rdt = i_wb_cpu_rdt;
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assign o_wb_cpu_ibus_ack = i_wb_cpu_ack & i_wb_cpu_ibus_cyc;
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assign o_wb_cpu_adr = i_wb_cpu_ibus_cyc ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr;
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assign o_wb_cpu_dat = i_wb_cpu_dbus_dat;
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assign o_wb_cpu_sel = i_wb_cpu_dbus_sel;
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assign o_wb_cpu_we = i_wb_cpu_dbus_we & !i_wb_cpu_ibus_cyc;
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assign o_wb_cpu_cyc = i_wb_cpu_ibus_cyc | i_wb_cpu_dbus_cyc;
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endmodule
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