mirror of
https://github.com/olofk/serv.git
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96 lines
2.7 KiB
Verilog
96 lines
2.7 KiB
Verilog
`default_nettype none
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module servant_orangecrab
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(
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input wire clk,
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input wire btn,
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output wire r,
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output wire g,
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output wire b,
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output wire tx
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);
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parameter memfile = "zephyr_hello.hex";
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parameter memsize = 8192;
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wire wb_clk;
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wire pll_locked;
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EHXPLLL #(
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.CLKI_DIV(6),
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.CLKFB_DIV(4),
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.CLKOP_DIV(15),
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.CLKOS_DIV(8),
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.CLKOS2_DIV(8),
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.CLKOS3_DIV(8),
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.CLKOP_ENABLE("ENABLED"),
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.CLKOS_ENABLE("DISABLED"),
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.CLKOS2_ENABLE("DISABLED"),
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.CLKOS3_ENABLE("DISABLED"),
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.CLKOP_CPHASE(0),
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.CLKOS_CPHASE(0),
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.CLKOS2_CPHASE(0),
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.CLKOS3_CPHASE(0),
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.CLKOP_FPHASE(0),
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.CLKOS_FPHASE(0),
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.CLKOS2_FPHASE(0),
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.CLKOS3_FPHASE(0),
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.FEEDBK_PATH("CLKOP"),
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.CLKOP_TRIM_POL("RISING"),
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.CLKOP_TRIM_DELAY(0),
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.CLKOS_TRIM_POL("RISING"),
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.CLKOS_TRIM_DELAY(0),
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.OUTDIVIDER_MUXA("DIVA"),
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.OUTDIVIDER_MUXB("DIVB"),
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.OUTDIVIDER_MUXC("DIVC"),
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.OUTDIVIDER_MUXD("DIVD"),
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.PLL_LOCK_MODE(0),
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.PLL_LOCK_DELAY(200),
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.STDBY_ENABLE("DISABLED"),
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.REFIN_RESET("DISABLED"),
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.SYNC_ENABLE("DISABLED"),
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.INT_LOCK_STICKY("ENABLED"),
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.DPHASE_SOURCE("DISABLED"),
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.PLLRST_ENA("DISABLED"),
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.INTFB_WAKE("DISABLED")
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) uPLL (
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.CLKI(clk), // ref input
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.CLKFB(wb_clk), // ext fb input
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.PHASESEL1(0), // msbit phs adj select
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.PHASESEL0(0), // lsbit phs adj select
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.PHASEDIR(0), // phs adj dir
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.PHASESTEP(0), // phs adj step
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.PHASELOADREG(0), // load phs adj
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.STDBY(0), // power down pll
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.PLLWAKESYNC(0), // int/ext fb switching @ wakeup
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.RST(0), // pll reset
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.ENCLKOP(1), // primary output enable
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.ENCLKOS(0), // secondary output enable
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.ENCLKOS2(0), // secondary output enable
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.ENCLKOS3(0), // secondary output enable
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.CLKOP(wb_clk), // primary output
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.CLKOS(), // secondary output
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.CLKOS2(), // secondary output
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.CLKOS3(), // secondary output
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.LOCK(pll_locked), // lock indicator
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.INTLOCK(), // internal lock indictor
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.REFCLK(), // output of ref select mux
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.CLKINTFB() // internal fb
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);
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reg wb_rst;
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always @(posedge wb_clk)
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wb_rst <= ~pll_locked;
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wire q;
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servant
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#(.memfile (memfile),
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.memsize (memsize))
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servant
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(.wb_clk (wb_clk),
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.wb_rst (wb_rst),
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.q (q));
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assign r = q;
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assign g = q;
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assign b = q;
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assign tx = q;
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endmodule
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