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37 lines
866 B
Verilog
37 lines
866 B
Verilog
`default_nettype none
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module servant_timer
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#(parameter WIDTH = 16,
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parameter RESET_STRATEGY = "",
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parameter DIVIDER = 0)
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(input wire i_clk,
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input wire i_rst,
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output reg o_irq,
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input wire [31:0] i_wb_dat,
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input wire i_wb_we,
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input wire i_wb_cyc,
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output reg [31:0] o_wb_dat);
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localparam HIGH = WIDTH-1-DIVIDER;
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reg [WIDTH-1:0] mtime;
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reg [HIGH:0] mtimecmp;
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wire [HIGH:0] mtimeslice = mtime[WIDTH-1:DIVIDER];
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always @(mtimeslice) begin
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o_wb_dat = 32'd0;
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o_wb_dat[HIGH:0] = mtimeslice;
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end
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always @(posedge i_clk) begin
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if (i_wb_cyc & i_wb_we)
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mtimecmp <= i_wb_dat[HIGH:0];
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mtime <= mtime + 'd1;
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o_irq <= (mtimeslice >= mtimecmp);
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if (RESET_STRATEGY != "NONE")
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if (i_rst) begin
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mtime <= 0;
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mtimecmp <= 0;
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end
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end
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endmodule
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