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34 lines
673 B
Verilog
34 lines
673 B
Verilog
`default_nettype none
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module servive_clock_gen
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(input wire i_clk,
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input wire i_rst,
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output wire o_clk,
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output wire o_rst);
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wire locked;
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reg [9:0] r;
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assign o_rst = r[9];
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always @(posedge o_clk)
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if (locked)
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r <= {r[8:0],1'b0};
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else
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r <= 10'b1111111111;
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wire [5:0] clk;
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assign o_clk = clk[0];
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altpll
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#(.operation_mode ("NORMAL"),
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.clk0_divide_by (25),
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.clk0_multiply_by (8),
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.inclk0_input_frequency (20000))
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pll
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(.areset (i_rst),
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.inclk ({1'b0, i_clk}),
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.clk (clk),
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.locked (locked));
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endmodule
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