mirror of
https://github.com/olofk/serv.git
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79 lines
2.4 KiB
Verilog
79 lines
2.4 KiB
Verilog
/* serving_ram.v : Shared RF I/D SRAM for the serving SoC
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*
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* ISC License
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*
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* Copyright (C) 2020 Olof Kindgren <olof.kindgren@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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`default_nettype none
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module serving_ram
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#(//Memory parameters
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parameter depth = 256,
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parameter aw = $clog2(depth),
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parameter memfile = "")
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(input wire i_clk,
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input wire [aw-1:0] i_waddr,
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input wire [7:0] i_wdata,
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input wire i_wen,
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input wire [aw-1:0] i_raddr,
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output wire [7:0] o_rdata,
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input wire [aw-1:2] i_wb_adr,
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input wire [31:0] i_wb_dat,
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input wire [3:0] i_wb_sel,
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input wire i_wb_we,
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input wire i_wb_stb,
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output wire [31:0] o_wb_rdt,
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output reg o_wb_ack);
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reg [1:0] bsel;
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reg [7:0] rdata;
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wire wb_en = i_wb_stb & !i_wen & !o_wb_ack;
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wire wb_we = i_wb_we & i_wb_sel[bsel];
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wire we = wb_en ? wb_we : i_wen;
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reg [7:0] mem [0:depth-1] /* verilator public */;
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wire [aw-1:0] waddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_waddr;
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wire [7:0] wdata = wb_en ? i_wb_dat[bsel*8+:8] : i_wdata;
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wire [aw-1:0] raddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_raddr;
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reg [23:0] wb_rdt;
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assign o_wb_rdt = {rdata, wb_rdt};
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always @(posedge i_clk) begin
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if (wb_en) bsel <= bsel + 2'd1;
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o_wb_ack <= wb_en & &bsel;
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if (bsel == 2'b01) wb_rdt[7:0] <= rdata;
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if (bsel == 2'b10) wb_rdt[15:8] <= rdata;
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if (bsel == 2'b11) wb_rdt[23:16] <= rdata;
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end
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always @(posedge i_clk) begin
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if (we) mem[waddr] <= wdata;
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rdata <= mem[raddr];
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end
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initial
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if(|memfile) begin
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$display("Preloading %m from %s", memfile);
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$readmemh(memfile, mem);
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end
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assign o_rdata = rdata;
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endmodule
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