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30 lines
674 B
Verilog
30 lines
674 B
Verilog
`default_nettype none
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module ser_shift
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(
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input wire i_clk,
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input wire i_load,
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input wire [4:0] i_shamt,
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input wire i_shamt_msb,
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input wire i_signbit,
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input wire i_right,
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output wire o_done,
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input wire i_d,
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output wire o_q);
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reg signbit;
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reg [5:0] cnt;
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reg wrapped;
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always @(posedge i_clk) begin
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cnt <= cnt + 6'd1;
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if (i_load) begin
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cnt <= 6'd0;
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signbit <= i_signbit & i_right;
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end
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wrapped <= cnt[5] | (i_shamt_msb & !i_right);
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end
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assign o_done = (cnt[4:0] == i_shamt);
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assign o_q = (i_right^wrapped) ? i_d : signbit;
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endmodule
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