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18 lines
307 B
Verilog
18 lines
307 B
Verilog
module uart_decoder
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#(parameter BAUD_RATE = 115200)
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(input rx);
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localparam T = 1000000000/BAUD_RATE;
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integer i;
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reg [7:0] ch;
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initial forever begin
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@(negedge rx);
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#(T/2) ch = 0;
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for (i=0;i<8;i=i+1)
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#T ch[i] = rx;
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$write("%c",ch);
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$fflush;
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end
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endmodule
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