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28 lines
281 B
Verilog
28 lines
281 B
Verilog
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module CV_96 (
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output q,
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output uart_txd
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);
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wire clk;
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HPS u0(
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.h2f_user0_clk( clk) //hps_0_h2f_user0_clock.clk
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);
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servive u1 (
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.i_clk ( clk ),
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.i_rst_n ( 1'b1),
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.q ( q ),
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.uart_txd( uart_txd )
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);
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endmodule
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