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37 lines
901 B
Verilog
37 lines
901 B
Verilog
`default_nettype none
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module servant_sim
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(input wire wb_clk,
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input wire wb_rst,
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output wire [31:0] pc_adr,
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output wire pc_vld,
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output wire q);
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parameter memfile = "";
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parameter memsize = 8192;
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parameter width = 1;
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parameter with_csr = 1;
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parameter compressed = 0;
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parameter align = compressed;
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reg [1023:0] firmware_file;
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initial
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if ($value$plusargs("firmware=%s", firmware_file)) begin
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$display("Loading RAM from %0s", firmware_file);
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$readmemh(firmware_file, dut.ram.mem);
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end
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servant
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#(.memfile (memfile),
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.memsize (memsize),
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.width (width),
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.debug (1'b1),
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.sim (1),
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.with_csr (with_csr),
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.compress (compressed[0:0]),
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.align (align[0:0]))
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dut(wb_clk, wb_rst, q);
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assign pc_adr = dut.wb_mem_adr;
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assign pc_vld = dut.wb_mem_ack;
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endmodule
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