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42 lines
1.4 KiB
ReStructuredText
42 lines
1.4 KiB
ReStructuredText
Overview
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========
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The SERV RISC-V CPU is an award-winning and highly compact processor core based on the RISC-V instruction set architecture (ISA). It is designed to be the smallest possible RISC-V compliant CPU and is particularly well-suited for embedded systems and applications where silicon area is critical.
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Key Features
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------------
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* **ISA:** RISC-V RV32IZifencei
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* **Optional ISA extensions:** C, M, Zicsr
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* **Optional features:** Timer interrupts, Extension interface
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* **Architecture:** Bit-serial (one bit processed per clock cycle)
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* **License:** ISC (available under other commercial licenses upon request)
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* **OS support:** Zephyr 3.7
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* **SW support:** Compatible with standard RISC-V toolchains
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* **Area:** Smallest RISC-V core available
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Applications
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------------
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* **Embedded Systems:** Ideal for minimalistic embedded control tasks
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* **IoT Devices:** Suitable for Internet of Things devices where space and power are limited
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* **Education:** Excellent resource for teaching and understanding the RISC-V architecture and CPU design
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* **Research:** Platform for research in minimalistic computing designs and for bringing up new fabrication processes
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Area
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----
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.. list-table:: Area for minimal configuration [#]_
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:widths: 25 25 25 25
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:header-rows: 1
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* - Lattice iCE40
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- Altera Cyclone10LP
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- AMD Artix-7
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- CMOS
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* - 198LUT/164FF
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- 239LUT/164FF
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- 125LUT/164FF
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- 2.1kGE
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.. [#] Excluding register file
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