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https://github.com/olofk/serv.git
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132 lines
3.6 KiB
Verilog
132 lines
3.6 KiB
Verilog
`default_nettype none
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module serv_synth_wrapper
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#(
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/* Register signals before or after the decoder
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0 : Register after the decoder. Faster but uses more resources
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1 : (default) Register before the decoder. Slower but uses less resources
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*/
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parameter PRE_REGISTER = 1,
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/* Amount of reset applied to design
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"NONE" : No reset at all. Relies on a POR to set correct initialization
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values and that core isn't reset during runtime
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"MINI" : Standard setting. Resets the minimal amount of FFs needed to
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restart execution from the instruction at RESET_PC
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*/
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parameter RESET_STRATEGY = "MINI",
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parameter WITH_CSR = 1,
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parameter RF_WIDTH = 2,
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parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH))
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(
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input wire clk,
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input wire i_rst,
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input wire i_timer_irq,
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output wire [31:0] o_ibus_adr,
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output wire o_ibus_cyc,
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input wire [31:0] i_ibus_rdt,
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input wire i_ibus_ack,
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output wire [31:0] o_dbus_adr,
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output wire [31:0] o_dbus_dat,
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output wire [3:0] o_dbus_sel,
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output wire o_dbus_we ,
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output wire o_dbus_cyc,
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input wire [31:0] i_dbus_rdt,
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input wire i_dbus_ack,
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output wire [RF_L2D-1:0] o_waddr,
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output wire [RF_WIDTH-1:0] o_wdata,
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output wire o_wen,
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output wire [RF_L2D-1:0] o_raddr,
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input wire [RF_WIDTH-1:0] i_rdata);
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localparam CSR_REGS = WITH_CSR*4;
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wire rf_wreq;
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wire rf_rreq;
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wire [4+WITH_CSR:0] wreg0;
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wire [4+WITH_CSR:0] wreg1;
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wire wen0;
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wire wen1;
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wire wdata0;
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wire wdata1;
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wire [4+WITH_CSR:0] rreg0;
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wire [4+WITH_CSR:0] rreg1;
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wire rf_ready;
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wire rdata0;
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wire rdata1;
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serv_rf_ram_if
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#(.width (RF_WIDTH),
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.reset_strategy (RESET_STRATEGY),
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.csr_regs (CSR_REGS))
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rf_ram_if
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(.i_clk (clk),
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.i_rst (i_rst),
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.i_wreq (rf_wreq),
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.i_rreq (rf_rreq),
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.o_ready (rf_ready),
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.i_wreg0 (wreg0),
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.i_wreg1 (wreg1),
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.i_wen0 (wen0),
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.i_wen1 (wen1),
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.i_wdata0 (wdata0),
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.i_wdata1 (wdata1),
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.i_rreg0 (rreg0),
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.i_rreg1 (rreg1),
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.o_rdata0 (rdata0),
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.o_rdata1 (rdata1),
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.o_waddr (o_waddr),
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.o_wdata (o_wdata),
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.o_wen (o_wen),
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.o_raddr (o_raddr),
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.i_rdata (i_rdata));
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serv_top
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#(.RESET_PC (32'd0),
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.PRE_REGISTER (PRE_REGISTER),
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.RESET_STRATEGY (RESET_STRATEGY),
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.WITH_CSR (WITH_CSR),
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.MDU(1'b0))
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cpu
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(
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.clk (clk),
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.i_rst (i_rst),
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.i_timer_irq (i_timer_irq),
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.o_rf_rreq (rf_rreq),
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.o_rf_wreq (rf_wreq),
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.i_rf_ready (rf_ready),
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.o_wreg0 (wreg0),
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.o_wreg1 (wreg1),
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.o_wen0 (wen0),
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.o_wen1 (wen1),
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.o_wdata0 (wdata0),
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.o_wdata1 (wdata1),
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.o_rreg0 (rreg0),
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.o_rreg1 (rreg1),
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.i_rdata0 (rdata0),
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.i_rdata1 (rdata1),
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.o_ibus_adr (o_ibus_adr),
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.o_ibus_cyc (o_ibus_cyc),
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.i_ibus_rdt (i_ibus_rdt),
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.i_ibus_ack (i_ibus_ack),
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.o_dbus_adr (o_dbus_adr),
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.o_dbus_dat (o_dbus_dat),
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.o_dbus_sel (o_dbus_sel),
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.o_dbus_we (o_dbus_we),
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.o_dbus_cyc (o_dbus_cyc),
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.i_dbus_rdt (i_dbus_rdt),
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.i_dbus_ack (i_dbus_ack),
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//Extension
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.o_ext_funct3 (),
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.i_ext_ready (1'b0),
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.i_ext_rd (32'd0),
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.o_ext_rs1 (),
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.o_ext_rs2 (),
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//MDU
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.o_mdu_valid ());
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endmodule
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`default_nettype wire
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