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45 lines
1.5 KiB
Verilog
45 lines
1.5 KiB
Verilog
/* serving_ram.v : I/D SRAM for the serving SoC
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*
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* ISC License
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*
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* Copyright (C) 2020 Olof Kindgren <olof.kindgren@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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`default_nettype none
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module serving_ram
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#(//Memory parameters
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parameter depth = 256,
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parameter aw = $clog2(depth),
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parameter memfile = "")
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(input wire i_clk,
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input wire [aw-1:0] i_waddr,
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input wire [7:0] i_wdata,
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input wire i_wen,
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input wire [aw-1:0] i_raddr,
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output reg [7:0] o_rdata);
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reg [7:0] mem [0:depth-1] /* verilator public */;
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always @(posedge i_clk) begin
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if (i_wen) mem[i_waddr] <= i_wdata;
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o_rdata <= mem[i_raddr];
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end
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initial
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if(|memfile) begin
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$display("Preloading %m from %s", memfile);
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$readmemh(memfile, mem);
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end
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endmodule
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