mirror of
https://github.com/olofk/serv.git
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66 lines
2.2 KiB
Verilog
66 lines
2.2 KiB
Verilog
/* serving_mux.v : Simple Wishbone mux for the serving SoC
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*
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* ISC License
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*
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* Copyright (C) 2020 Olof Kindgren <olof.kindgren@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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module serving_mux
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(
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input wire i_clk,
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input wire i_rst,
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input wire [31:0] i_wb_cpu_adr,
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input wire [31:0] i_wb_cpu_dat,
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input wire [3:0] i_wb_cpu_sel,
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input wire i_wb_cpu_we,
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input wire i_wb_cpu_stb,
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output wire [31:0] o_wb_cpu_rdt,
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output wire o_wb_cpu_ack,
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output wire [31:0] o_wb_mem_adr,
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output wire [31:0] o_wb_mem_dat,
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output wire [3:0] o_wb_mem_sel,
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output wire o_wb_mem_we,
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output wire o_wb_mem_stb,
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input wire [31:0] i_wb_mem_rdt,
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input wire i_wb_mem_ack,
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output wire [31:0] o_wb_ext_adr,
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output wire [31:0] o_wb_ext_dat,
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output wire [3:0] o_wb_ext_sel,
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output wire o_wb_ext_we,
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output wire o_wb_ext_stb,
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input wire [31:0] i_wb_ext_rdt,
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input wire i_wb_ext_ack);
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wire ext = (i_wb_cpu_adr[31:30] != 2'b00);
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assign o_wb_cpu_rdt = ext ? i_wb_ext_rdt : i_wb_mem_rdt;
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assign o_wb_cpu_ack = ext ? i_wb_ext_ack : i_wb_mem_ack;
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assign o_wb_mem_adr = i_wb_cpu_adr;
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assign o_wb_mem_dat = i_wb_cpu_dat;
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assign o_wb_mem_sel = i_wb_cpu_sel;
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assign o_wb_mem_we = i_wb_cpu_we;
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assign o_wb_mem_stb = i_wb_cpu_stb & !ext;
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assign o_wb_ext_adr = i_wb_cpu_adr;
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assign o_wb_ext_dat = i_wb_cpu_dat;
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assign o_wb_ext_sel = i_wb_cpu_sel;
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assign o_wb_ext_we = i_wb_cpu_we;
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assign o_wb_ext_stb = i_wb_cpu_stb & ext;
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endmodule
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