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8edd456b5d
This adds some optimizations to serv_rf_ram_if. It also adds a read enable signal and delays writes one cycle which has the added bonus that no reads or writes happen in the same cycle for RF_WIDTH > 2. This allows SERV to be used with single-port RAMs in most cases.
45 lines
1.2 KiB
Verilog
45 lines
1.2 KiB
Verilog
module serv_rf_ram
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#(parameter width=0,
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parameter csr_regs=4,
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parameter depth=32*(32+csr_regs)/width)
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(input wire i_clk,
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input wire [$clog2(depth)-1:0] i_waddr,
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input wire [width-1:0] i_wdata,
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input wire i_wen,
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input wire [$clog2(depth)-1:0] i_raddr,
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input wire i_ren,
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output wire [width-1:0] o_rdata);
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reg [width-1:0] memory [0:depth-1];
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reg [width-1:0] rdata ;
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always @(posedge i_clk) begin
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if (i_wen)
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memory[i_waddr] <= i_wdata;
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rdata <= i_ren ? memory[i_raddr] : {width{1'bx}};
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end
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/* Reads from reg x0 needs to return 0
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Check that the part of the read address corresponding to the register
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is zero and gate the output
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width LSB of reg index $clog2(width)
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2 4 1
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4 3 2
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8 2 3
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16 1 4
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32 0 5
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*/
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reg regzero;
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always @(posedge i_clk)
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regzero <= !(|i_raddr[$clog2(depth)-1:5-$clog2(width)]);
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assign o_rdata = rdata & ~{width{regzero}};
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`ifdef SERV_CLEAR_RAM
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integer i;
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initial
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for (i=0;i<depth;i=i+1)
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memory[i] = {width{1'd0}};
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`endif
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endmodule
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