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References: - https://github.com/fusesoc/blinky/pull/68/files (EBAZ4205 blinky) - https://github.com/fusesoc/blinky#ebaz4205-development-board - Existing 'arty_a7_35t' example This PR also cleans up a bunch of whitespace issues (no functional change).
10 lines
465 B
Tcl
10 lines
465 B
Tcl
## 33.333 MHz Clock signal
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set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports i_clk];
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create_clock -add -name sys_clk_pin -period 30.00 -waveform {0 5} [get_ports i_clk];
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## LED(s)
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# set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { q_green }];
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# set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { q }];
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## UART on DATA1_8 pin
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set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports q];
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