mirror of
https://github.com/olofk/serv.git
synced 2025-04-24 22:07:20 -04:00
128 lines
2.7 KiB
C++
128 lines
2.7 KiB
C++
#include <stdint.h>
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#include <signal.h>
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#include "verilated_vcd_c.h"
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#include "Vservant.h"
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using namespace std;
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static bool done;
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vluint64_t main_time = 0; // Current simulation time
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// This is a 64-bit integer to reduce wrap over issues and
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// allow modulus. You can also use a double, if you wish.
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double sc_time_stamp () { // Called by $time in Verilog
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return main_time; // converts to double, to match
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// what SystemC does
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}
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void INThandler(int signal)
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{
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printf("\nCaught ctrl-c\n");
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done = true;
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}
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typedef struct {
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bool last_value;
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} gpio_context_t;
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void do_gpio(gpio_context_t *context, bool gpio) {
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if (context->last_value != gpio) {
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context->last_value = gpio;
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printf("%lu output q is %s\n", main_time, gpio ? "ON" : "OFF");
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}
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}
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typedef struct {
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uint8_t state;
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char ch;
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uint32_t baud_t;
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vluint64_t last_update;
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} uart_context_t;
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void uart_init(uart_context_t *context, uint32_t baud_rate) {
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context->baud_t = 1000*1000*1000/baud_rate;
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}
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void do_uart(uart_context_t *context, bool rx) {
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if (context->state == 0) {
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if (!rx) {
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context->last_update = main_time + context->baud_t/2;
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context->state++;
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}
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}
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else if(context->state == 1) {
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if (main_time > context->last_update) {
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context->last_update += context->baud_t;
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context->ch = 0;
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context->state++;
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}
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}
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else if (context->state < 10) {
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if (main_time > context->last_update) {
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context->last_update += context->baud_t;
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context->ch |= rx << (context->state-2);
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context->state++;
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}
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}
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else {
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if (main_time > context->last_update) {
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context->last_update += context->baud_t;
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putchar(context->ch);
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context->state=0;
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}
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}
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}
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int main(int argc, char **argv, char **env)
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{
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vluint64_t sample_time = 0;
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uint32_t insn = 0;
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uint32_t ex_pc = 0;
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int baud_rate = 0;
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gpio_context_t gpio_context;
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uart_context_t uart_context;
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Verilated::commandArgs(argc, argv);
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Vservant* top = new Vservant;
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const char *arg = Verilated::commandArgsPlusMatch("uart_baudrate=");
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if (arg[0]) {
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baud_rate = atoi(arg+15);
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if (baud_rate) {
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uart_init(&uart_context, baud_rate);
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}
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}
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VerilatedVcdC * tfp = 0;
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const char *vcd = Verilated::commandArgsPlusMatch("vcd=");
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if (vcd[0]) {
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Verilated::traceEverOn(true);
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tfp = new VerilatedVcdC;
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top->trace (tfp, 99);
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tfp->open ("trace.vcd");
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}
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signal(SIGINT, INThandler);
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top->wb_clk = 1;
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bool q = top->q;
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while (!(done || Verilated::gotFinish())) {
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top->wb_rst = main_time < 100;
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top->eval();
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if (tfp)
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tfp->dump(main_time);
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if (baud_rate)
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do_uart(&uart_context, top->q);
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else
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do_gpio(&gpio_context, top->q);
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top->wb_clk = !top->wb_clk;
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main_time+=31.25;
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}
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if (tfp)
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tfp->close();
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exit(0);
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}
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