serv/serv.core
2019-07-29 08:41:03 +02:00

46 lines
869 B
Text

CAPI=2:
name : ::serv:0
filesets:
core:
files:
- rtl/serv_params.vh : {is_include_file : true}
- rtl/shift_reg.v
- rtl/ser_add.v
- rtl/ser_lt.v
- rtl/ser_shift.v
- rtl/serv_bufreg.v
- rtl/serv_alu.v
- rtl/serv_csr.v
- rtl/serv_ctrl.v
- rtl/serv_decode.v
- rtl/serv_mem_if.v
- rtl/serv_regfile.v
- rtl/serv_mpram.v
- rtl/serv_top.v
file_type : verilogSource
targets:
default:
filesets : [core]
parameters : [RISCV_FORMAL, SERV_CLEAR_RAM]
toplevel : ["is_toplevel? (serv_top)"]
lint:
default_tool : verilator
filesets : [core]
tools:
verilator:
mode : lint-only
toplevel : serv_top
parameters:
RISCV_FORMAL:
datatype : bool
paramtype : vlogdefine
SERV_CLEAR_RAM:
datatype : bool
paramtype : vlogdefine