mirror of
https://github.com/olofk/serv.git
synced 2025-04-20 11:57:07 -04:00
232 lines
6.1 KiB
Verilog
232 lines
6.1 KiB
Verilog
/* serving.v : Top-level for the serving SoC
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*
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* ISC License
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*
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* Copyright (C) 2020 Olof Kindgren <olof.kindgren@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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`default_nettype none
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module serving
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(
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input wire i_clk,
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input wire i_rst,
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input wire i_timer_irq,
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output wire [31:0] o_wb_adr,
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output wire [31:0] o_wb_dat,
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output wire [3:0] o_wb_sel,
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output wire o_wb_we ,
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output wire o_wb_stb,
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input wire [31:0] i_wb_rdt,
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input wire i_wb_ack);
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parameter memfile = "";
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parameter memsize = 8192;
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parameter WITH_CSR = 1;
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localparam regs = 32+WITH_CSR*4;
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localparam rf_width = 8;
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localparam aw = $clog2(memsize);
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wire [31:0] wb_ibus_adr;
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wire wb_ibus_stb;
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wire [31:0] wb_ibus_rdt;
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wire wb_ibus_ack;
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wire [31:0] wb_dbus_adr;
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wire [31:0] wb_dbus_dat;
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wire [3:0] wb_dbus_sel;
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wire wb_dbus_we;
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wire wb_dbus_stb;
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wire [31:0] wb_dbus_rdt;
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wire wb_dbus_ack;
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wire [31:0] wb_dmem_adr;
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wire [31:0] wb_dmem_dat;
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wire [3:0] wb_dmem_sel;
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wire wb_dmem_we;
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wire wb_dmem_stb;
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wire [31:0] wb_dmem_rdt;
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wire wb_dmem_ack;
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wire [31:0] wb_mem_adr;
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wire [31:0] wb_mem_dat;
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wire [3:0] wb_mem_sel;
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wire wb_mem_we;
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wire wb_mem_stb;
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wire [31:0] wb_mem_rdt;
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wire wb_mem_ack;
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wire [6+WITH_CSR:0] waddr;
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wire [rf_width-1:0] wdata;
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wire wen;
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wire [6+WITH_CSR:0] raddr;
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wire [rf_width-1:0] rdata;
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wire [aw-1:0] rf_waddr = ~{{aw-2-5-WITH_CSR{1'b0}},waddr};
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wire [aw-1:0] rf_raddr = ~{{aw-2-5-WITH_CSR{1'b0}},raddr};
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serving_arbiter arbiter
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(.i_wb_cpu_dbus_adr (wb_dmem_adr),
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.i_wb_cpu_dbus_dat (wb_dmem_dat),
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.i_wb_cpu_dbus_sel (wb_dmem_sel),
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.i_wb_cpu_dbus_we (wb_dmem_we ),
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.i_wb_cpu_dbus_stb (wb_dmem_stb),
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.o_wb_cpu_dbus_rdt (wb_dmem_rdt),
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.o_wb_cpu_dbus_ack (wb_dmem_ack),
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.i_wb_cpu_ibus_adr (wb_ibus_adr),
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.i_wb_cpu_ibus_stb (wb_ibus_stb),
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.o_wb_cpu_ibus_rdt (wb_ibus_rdt),
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.o_wb_cpu_ibus_ack (wb_ibus_ack),
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.o_wb_mem_adr (wb_mem_adr),
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.o_wb_mem_dat (wb_mem_dat),
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.o_wb_mem_sel (wb_mem_sel),
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.o_wb_mem_we (wb_mem_we ),
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.o_wb_mem_stb (wb_mem_stb),
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.i_wb_mem_rdt (wb_mem_rdt),
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.i_wb_mem_ack (wb_mem_ack));
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serving_mux mux
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(.i_clk (i_clk),
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.i_rst (i_rst),
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.i_wb_cpu_adr (wb_dbus_adr),
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.i_wb_cpu_dat (wb_dbus_dat),
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.i_wb_cpu_sel (wb_dbus_sel),
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.i_wb_cpu_we (wb_dbus_we),
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.i_wb_cpu_stb (wb_dbus_stb),
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.o_wb_cpu_rdt (wb_dbus_rdt),
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.o_wb_cpu_ack (wb_dbus_ack),
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.o_wb_mem_adr (wb_dmem_adr),
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.o_wb_mem_dat (wb_dmem_dat),
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.o_wb_mem_sel (wb_dmem_sel),
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.o_wb_mem_we (wb_dmem_we),
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.o_wb_mem_stb (wb_dmem_stb),
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.i_wb_mem_rdt (wb_dmem_rdt),
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.i_wb_mem_ack (wb_dmem_ack),
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.o_wb_ext_adr (o_wb_adr),
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.o_wb_ext_dat (o_wb_dat),
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.o_wb_ext_sel (o_wb_sel),
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.o_wb_ext_we (o_wb_we),
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.o_wb_ext_stb (o_wb_stb),
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.i_wb_ext_rdt (i_wb_rdt),
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.i_wb_ext_ack (i_wb_ack));
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serving_ram
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#(.memfile (memfile),
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.depth (memsize))
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ram
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(// Wishbone interface
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.i_clk (i_clk),
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.i_waddr (rf_waddr),
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.i_wdata (wdata),
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.i_wen (wen),
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.i_raddr (rf_raddr),
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.o_rdata (rdata),
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.i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
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.i_wb_stb (wb_mem_stb),
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.i_wb_we (wb_mem_we) ,
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.i_wb_sel (wb_mem_sel),
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.i_wb_dat (wb_mem_dat),
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.o_wb_rdt (wb_mem_rdt),
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.o_wb_ack (wb_mem_ack));
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localparam RF_L2W = $clog2(rf_width);
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wire rf_wreq;
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wire rf_rreq;
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wire [$clog2(regs)-1:0] wreg0;
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wire [$clog2(regs)-1:0] wreg1;
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wire wen0;
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wire wen1;
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wire wdata0;
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wire wdata1;
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wire [$clog2(regs)-1:0] rreg0;
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wire [$clog2(regs)-1:0] rreg1;
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wire rf_ready;
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wire rdata0;
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wire rdata1;
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serv_rf_ram_if
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#(.width (rf_width),
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.csr_regs (WITH_CSR*4))
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rf_ram_if
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(.i_clk (i_clk),
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.i_rst (i_rst),
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.i_wreq (rf_wreq),
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.i_rreq (rf_rreq),
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.o_ready (rf_ready),
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.i_wreg0 (wreg0),
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.i_wreg1 (wreg1),
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.i_wen0 (wen0),
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.i_wen1 (wen1),
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.i_wdata0 (wdata0),
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.i_wdata1 (wdata1),
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.i_rreg0 (rreg0),
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.i_rreg1 (rreg1),
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.o_rdata0 (rdata0),
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.o_rdata1 (rdata1),
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.o_waddr (waddr),
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.o_wdata (wdata),
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.o_wen (wen),
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.o_raddr (raddr),
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.i_rdata (rdata));
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serv_top
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#(.RESET_PC (32'h0000_0000),
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.WITH_CSR (WITH_CSR))
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cpu
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(
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.clk (i_clk),
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.i_rst (i_rst),
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.i_timer_irq (i_timer_irq),
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//RF IF
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.o_rf_rreq (rf_rreq),
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.o_rf_wreq (rf_wreq),
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.i_rf_ready (rf_ready),
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.o_wreg0 (wreg0),
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.o_wreg1 (wreg1),
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.o_wen0 (wen0),
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.o_wen1 (wen1),
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.o_wdata0 (wdata0),
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.o_wdata1 (wdata1),
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.o_rreg0 (rreg0),
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.o_rreg1 (rreg1),
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.i_rdata0 (rdata0),
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.i_rdata1 (rdata1),
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//Instruction bus
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.o_ibus_adr (wb_ibus_adr),
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.o_ibus_cyc (wb_ibus_stb),
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.i_ibus_rdt (wb_ibus_rdt),
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.i_ibus_ack (wb_ibus_ack),
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//Data bus
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.o_dbus_adr (wb_dbus_adr),
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.o_dbus_dat (wb_dbus_dat),
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.o_dbus_sel (wb_dbus_sel),
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.o_dbus_we (wb_dbus_we),
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.o_dbus_cyc (wb_dbus_stb),
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.i_dbus_rdt (wb_dbus_rdt),
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.i_dbus_ack (wb_dbus_ack));
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endmodule
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