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38 lines
932 B
Verilog
38 lines
932 B
Verilog
module pll(input clki,
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output locked,
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output clko
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);
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wire clkfb;
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wire clkos;
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wire clkop;
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(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
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EHXPLLL #(
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.PLLRST_ENA("DISABLED"),
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.INTFB_WAKE("DISABLED"),
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.STDBY_ENABLE("DISABLED"),
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.DPHASE_SOURCE("DISABLED"),
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.CLKOP_FPHASE(0),
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.CLKOP_CPHASE(18),
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.OUTDIVIDER_MUXA("DIVA"),
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.CLKOP_ENABLE("ENABLED"),
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.CLKOP_DIV(38),
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.CLKFB_DIV(5),
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.CLKI_DIV(8),
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.FEEDBK_PATH("INT_OP")
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) pll_i (
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.CLKI(clki),
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.CLKFB(clkfb),
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.CLKINTFB(clkfb),
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.CLKOP(clkop),
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.RST(1'b0),
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.STDBY(1'b0),
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.PHASESEL0(1'b0),
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.PHASESEL1(1'b0),
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.PHASEDIR(1'b0),
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.PHASESTEP(1'b0),
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.PLLWAKESYNC(1'b0),
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.ENCLKOP(1'b0),
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.LOCK(locked)
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);
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assign clko = clkop;
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endmodule
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