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bram reset bug fix

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This commit is contained in:
tinebp 2025-01-20 22:16:05 -08:00
parent fce24b9535
commit 001a107395
4 changed files with 34 additions and 32 deletions
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31
hw/rtl/libs/VX_dp_ram.sv
View file

@ -26,21 +26,25 @@
end \
end
`define RAM_WRITE_ALL if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
`ifdef SIMULATION
`define RAM_RESET_BLOCK if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else
`endif
`define RAM_RESET_BLOCK
`endif
`define RAM_WRITE_ALL `RAM_RESET_BLOCK \
if (write) begin \
ram[waddr] <= wdata; \
end
`ifdef QUARTUS
`define RAM_ARRAY_WREN reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`define RAM_WRITE_WREN if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
`define RAM_WRITE_WREN `RAM_RESET_BLOCK \
if (write) begin \
for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[waddr][i] <= wdata[i * WSELW +: WSELW]; \
@ -49,11 +53,8 @@
end
`else
`define RAM_ARRAY_WREN reg [DATAW-1:0] ram [0:SIZE-1];
`define RAM_WRITE_WREN if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
`define RAM_WRITE_WREN `RAM_RESET_BLOCK \
if (write) begin \
for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \

31
hw/rtl/libs/VX_sp_ram.sv
View file

@ -26,21 +26,25 @@
end \
end
`define RAM_WRITE_ALL if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
`ifdef SIMULATION
`define RAM_RESET_BLOCK if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else
`endif
`define RAM_RESET_BLOCK
`endif
`define RAM_WRITE_ALL `RAM_RESET_BLOCK \
if (write) begin \
ram[addr] <= wdata; \
end
`ifdef QUARTUS
`define RAM_ARRAY_WREN reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`define RAM_WRITE_WREN if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
`define RAM_WRITE_WREN `RAM_RESET_BLOCK \
if (write) begin \
for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[addr][i] <= wdata[i * WSELW +: WSELW]; \
@ -49,11 +53,8 @@
end
`else
`define RAM_ARRAY_WREN reg [DATAW-1:0] ram [0:SIZE-1];
`define RAM_WRITE_WREN if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
`define RAM_WRITE_WREN `RAM_RESET_BLOCK \
if (write) begin \
for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \

2
hw/scripts/xilinx_async_bram_patch.tcl
View file

@ -508,7 +508,7 @@ proc replace_net_source {net source_pin} {
exit -1
}
set external_net [get_nets -of_objects $pin]
set external_net [get_nets -quiet -of_objects $pin]
if {[llength $external_net] == 0} {
# Connect pin to source net
connect_net -net $source_net -objects $pin -hierarchical

2
hw/syn/xilinx/dut/project.tcl
View file

@ -92,7 +92,7 @@ proc run_setup {} {
set_property top $top_module [current_fileset]
set_property \
-name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} \
-value {-mode out_of_context -flatten_hierarchy "rebuilt"} \
-value {-mode out_of_context} \
-objects [get_runs synth_1]
# register compilation hooks