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minor update

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This commit is contained in:
Blaise Tine 2023-03-18 16:49:42 -04:00
parent 5aa99d6643
commit 01b7cbdf32
6 changed files with 86 additions and 86 deletions
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16
hw/rtl/core/VX_csr_data.sv
View file

@ -61,7 +61,7 @@ module VX_csr_data #(
// CSRs Write /////////////////////////////////////////////////////////////
`ifdef EXT_F_ENABLE
reg [`NUM_WARPS-1:0][`INST_FRM_BITS+`FFLAGS_BITS-1:0] fcsr;
reg [`NUM_WARPS-1:0][`INST_FRM_BITS+`FP_FLAGS_BITS-1:0] fcsr;
`endif
reg [31:0] csr_satp;
@ -80,7 +80,7 @@ module VX_csr_data #(
fcsr <= '0;
end else begin
if (fpu_to_csr_if.write_enable) begin
fcsr[fpu_to_csr_if.write_wid][`FFLAGS_BITS-1:0] <= fcsr[fpu_to_csr_if.write_wid][`FFLAGS_BITS-1:0]
fcsr[fpu_to_csr_if.write_wid][`FP_FLAGS_BITS-1:0] <= fcsr[fpu_to_csr_if.write_wid][`FP_FLAGS_BITS-1:0]
| fpu_to_csr_if.write_fflags;
end
end
@ -88,9 +88,9 @@ module VX_csr_data #(
if (write_enable) begin
case (write_addr)
`ifdef EXT_F_ENABLE
`CSR_FFLAGS: fcsr[write_wid][`FFLAGS_BITS-1:0] <= write_data[`FFLAGS_BITS-1:0];
`CSR_FRM: fcsr[write_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS] <= write_data[`INST_FRM_BITS-1:0];
`CSR_FCSR: fcsr[write_wid] <= write_data[`FFLAGS_BITS+`INST_FRM_BITS-1:0];
`CSR_FFLAGS: fcsr[write_wid][`FP_FLAGS_BITS-1:0] <= write_data[`FP_FLAGS_BITS-1:0];
`CSR_FRM: fcsr[write_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS] <= write_data[`INST_FRM_BITS-1:0];
`CSR_FCSR: fcsr[write_wid] <= write_data[`FP_FLAGS_BITS+`INST_FRM_BITS-1:0];
`endif
`CSR_SATP: csr_satp <= write_data;
`CSR_MSTATUS: csr_mstatus <= write_data;
@ -120,8 +120,8 @@ module VX_csr_data #(
read_addr_valid_r = 1;
case (read_addr)
`ifdef EXT_F_ENABLE
`CSR_FFLAGS : read_data_rw_r = 32'(fcsr[read_wid][`FFLAGS_BITS-1:0]);
`CSR_FRM : read_data_rw_r = 32'(fcsr[read_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS]);
`CSR_FFLAGS : read_data_rw_r = 32'(fcsr[read_wid][`FP_FLAGS_BITS-1:0]);
`CSR_FRM : read_data_rw_r = 32'(fcsr[read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS]);
`CSR_FCSR : read_data_rw_r = 32'(fcsr[read_wid]);
`endif
`CSR_LWID : read_data_ro_r = 32'(read_wid);
@ -366,7 +366,7 @@ module VX_csr_data #(
`RUNTIME_ASSERT(~read_enable || read_addr_valid_r, ("%t: *** invalid CSR read address: 0x%0h (#%0d)", $time, read_addr, read_uuid))
`ifdef EXT_F_ENABLE
assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS];
assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS];
`endif
`ifdef PERF_ENABLE

2
hw/rtl/fpu_unit/VX_fpu_arb.sv
View file

@ -30,7 +30,7 @@ module VX_fpu_arb #(
localparam NUM_REQS = 1 << LOG_NUM_REQS;
localparam TAG_OUT_WIDTH = TAG_WIDTH + LOG_NUM_REQS;
localparam REQ_DATAW = TAG_OUT_WIDTH + `INST_FPU_BITS + `INST_FRM_BITS + NUM_LANES * 3 * 32;
localparam RSP_DATAW = TAG_WIDTH + NUM_LANES * (32 + `FFLAGS_BITS) + 1;
localparam RSP_DATAW = TAG_WIDTH + NUM_LANES * (32 + `FP_FLAGS_BITS) + 1;
///////////////////////////////////////////////////////////////////////

16
hw/rtl/fpu_unit/VX_fpu_class.sv
View file

@ -7,7 +7,7 @@ module VX_fpu_class # (
) (
input [EXP_BITS-1:0] exp_i,
input [MAN_BITS-1:0] man_i,
output fp_class_t clss_o
output fclass_t fclass_o
);
wire is_normal = (exp_i != '0) && (exp_i != '1);
wire is_zero = (exp_i == '0) && (man_i == '0);
@ -17,12 +17,12 @@ module VX_fpu_class # (
wire is_signaling = is_nan && ~man_i[MAN_BITS-1];
wire is_quiet = is_nan && ~is_signaling;
assign clss_o.is_normal = is_normal;
assign clss_o.is_zero = is_zero;
assign clss_o.is_subnormal = is_subnormal;
assign clss_o.is_inf = is_inf;
assign clss_o.is_nan = is_nan;
assign clss_o.is_quiet = is_quiet;
assign clss_o.is_signaling = is_signaling;
assign fclass_o.is_normal = is_normal;
assign fclass_o.is_zero = is_zero;
assign fclass_o.is_subnormal = is_subnormal;
assign fclass_o.is_inf = is_inf;
assign fclass_o.is_nan = is_nan;
assign fclass_o.is_quiet = is_quiet;
assign fclass_o.is_signaling = is_signaling;
endmodule

78
hw/rtl/fpu_unit/VX_fpu_cvt.sv
View file

@ -59,7 +59,7 @@ module VX_fpu_cvt #(
// Input processing
fp_class_t [NUM_LANES-1:0] fp_clss;
fclass_t [NUM_LANES-1:0] fclass;
for (genvar i = 0; i < NUM_LANES; ++i) begin
VX_fpu_class #(
@ -68,7 +68,7 @@ module VX_fpu_cvt #(
) fp_class (
.exp_i (dataa[i][30:23]),
.man_i (dataa[i][22:0]),
.clss_o (fp_clss[i])
.clss_o (fclass[i])
);
end
@ -83,9 +83,9 @@ module VX_fpu_cvt #(
wire fmt_sign = dataa[i][31];
wire int_sign = dataa[i][31] && is_signed;
assign int_mantissa = int_sign ? (-dataa[i]) : dataa[i];
assign fmt_mantissa = INT_MAN_WIDTH'({fp_clss[i].is_normal, dataa[i][MAN_BITS-1:0]});
assign fmt_mantissa = INT_MAN_WIDTH'({fclass[i].is_normal, dataa[i][MAN_BITS-1:0]});
assign fmt_exponent[i] = {1'b0, dataa[i][MAN_BITS +: EXP_BITS]} +
{1'b0, fp_clss[i].is_subnormal};
{1'b0, fclass[i].is_subnormal};
assign encoded_mant[i] = is_itof ? int_mantissa : fmt_mantissa;
assign input_sign[i] = is_itof ? int_sign : fmt_sign;
`IGNORE_WARNINGS_END
@ -98,22 +98,22 @@ module VX_fpu_cvt #(
wire is_itof_s0;
wire unsigned_s0;
wire [2:0] rnd_mode_s0;
fp_class_t [NUM_LANES-1:0] fp_clss_s0;
wire [NUM_LANES-1:0] input_sign_s0;
fclass_t [NUM_LANES-1:0] fclass_s0;
wire [NUM_LANES-1:0] input_sign_s0;
wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent_s0;
wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant_s0;
wire stall;
VX_pipe_register #(
.DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + NUM_LANES * ($bits(fp_class_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)),
.DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + NUM_LANES * ($bits(fclass_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)),
.RESETW (1)
) pipe_reg0 (
.clk (clk),
.reset (reset),
.enable (~stall),
.data_in ({valid_in, tag_in, is_itof, !is_signed, frm, fp_clss, input_sign, fmt_exponent, encoded_mant}),
.data_out ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fp_clss_s0, input_sign_s0, fmt_exponent_s0, encoded_mant_s0})
.data_in ({valid_in, tag_in, is_itof, !is_signed, frm, fclass, input_sign, fmt_exponent, encoded_mant}),
.data_out ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fclass_s0, input_sign_s0, fmt_exponent_s0, encoded_mant_s0})
);
// Normalization
@ -156,21 +156,21 @@ module VX_fpu_cvt #(
wire is_itof_s1;
wire unsigned_s1;
wire [2:0] rnd_mode_s1;
fp_class_t [NUM_LANES-1:0] fp_clss_s1;
wire [NUM_LANES-1:0] input_sign_s1;
wire [NUM_LANES-1:0] mant_is_zero_s1;
fclass_t [NUM_LANES-1:0] fclass_s1;
wire [NUM_LANES-1:0] input_sign_s1;
wire [NUM_LANES-1:0] mant_is_zero_s1;
wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_s1;
wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_s1;
VX_pipe_register #(
.DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + NUM_LANES * ($bits(fp_class_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)),
.DATAW (1 + TAGW + 1 + `INST_FRM_BITS + 1 + NUM_LANES * ($bits(fclass_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)),
.RESETW (1)
) pipe_reg1 (
.clk (clk),
.reset (reset),
.enable (~stall),
.data_in ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fp_clss_s0, input_sign_s0, mant_is_zero_s0, input_mant_s0, input_exp_s0}),
.data_out ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fp_clss_s1, input_sign_s1, mant_is_zero_s1, input_mant_s1, input_exp_s1})
.data_in ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fclass_s0, input_sign_s0, mant_is_zero_s0, input_mant_s0, input_exp_s0}),
.data_out ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fclass_s1, input_sign_s1, mant_is_zero_s1, input_mant_s1, input_exp_s1})
);
// Perform adjustments to mantissa and exponent
@ -237,22 +237,22 @@ module VX_fpu_cvt #(
wire is_itof_s2;
wire unsigned_s2;
wire [2:0] rnd_mode_s2;
fp_class_t [NUM_LANES-1:0] fp_clss_s2;
wire [NUM_LANES-1:0] mant_is_zero_s2;
wire [NUM_LANES-1:0] input_sign_s2;
fclass_t [NUM_LANES-1:0] fclass_s2;
wire [NUM_LANES-1:0] mant_is_zero_s2;
wire [NUM_LANES-1:0] input_sign_s2;
wire [NUM_LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant_s2;
wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s2;
wire [NUM_LANES-1:0] of_before_round_s2;
VX_pipe_register #(
.DATAW (1 + TAGW + 1 + 1 + `INST_FRM_BITS + NUM_LANES * ($bits(fp_class_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)),
.DATAW (1 + TAGW + 1 + 1 + `INST_FRM_BITS + NUM_LANES * ($bits(fclass_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)),
.RESETW (1)
) pipe_reg2 (
.clk (clk),
.reset (reset),
.enable (~stall),
.data_in ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fp_clss_s1, mant_is_zero_s1, input_sign_s1, destination_mant_s1, final_exp_s1, of_before_round_s1}),
.data_out ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, rnd_mode_s2, fp_clss_s2, mant_is_zero_s2, input_sign_s2, destination_mant_s2, final_exp_s2, of_before_round_s2})
.data_in ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fclass_s1, mant_is_zero_s1, input_sign_s1, destination_mant_s1, final_exp_s1, of_before_round_s1}),
.data_out ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, rnd_mode_s2, fclass_s2, mant_is_zero_s2, input_sign_s2, destination_mant_s2, final_exp_s2, of_before_round_s2})
);
wire [NUM_LANES-1:0] rounded_sign;
@ -306,22 +306,22 @@ module VX_fpu_cvt #(
wire [TAGW-1:0] tag_in_s3;
wire is_itof_s3;
wire unsigned_s3;
fp_class_t [NUM_LANES-1:0] fp_clss_s3;
wire [NUM_LANES-1:0] mant_is_zero_s3;
wire [NUM_LANES-1:0] input_sign_s3;
wire [NUM_LANES-1:0] rounded_sign_s3;
wire [NUM_LANES-1:0][31:0] rounded_abs_s3;
wire [NUM_LANES-1:0] of_before_round_s3;
fclass_t [NUM_LANES-1:0] fclass_s3;
wire [NUM_LANES-1:0] mant_is_zero_s3;
wire [NUM_LANES-1:0] input_sign_s3;
wire [NUM_LANES-1:0] rounded_sign_s3;
wire [NUM_LANES-1:0][31:0] rounded_abs_s3;
wire [NUM_LANES-1:0] of_before_round_s3;
VX_pipe_register #(
.DATAW (1 + TAGW + 1 + 1 + NUM_LANES * ($bits(fp_class_t) + 1 + 1 + 32 + 1 + 1)),
.DATAW (1 + TAGW + 1 + 1 + NUM_LANES * ($bits(fclass_t) + 1 + 1 + 32 + 1 + 1)),
.RESETW (1)
) pipe_reg3 (
.clk (clk),
.reset (reset),
.enable (~stall),
.data_in ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, fp_clss_s2, mant_is_zero_s2, input_sign_s2, rounded_abs, rounded_sign, of_before_round_s2}),
.data_out ({valid_in_s3, tag_in_s3, is_itof_s3, unsigned_s3, fp_clss_s3, mant_is_zero_s3, input_sign_s3, rounded_abs_s3, rounded_sign_s3, of_before_round_s3})
.data_in ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, fclass_s2, mant_is_zero_s2, input_sign_s2, rounded_abs, rounded_sign, of_before_round_s2}),
.data_out ({valid_in_s3, tag_in_s3, is_itof_s3, unsigned_s3, fclass_s3, mant_is_zero_s3, input_sign_s3, rounded_abs_s3, rounded_sign_s3, of_before_round_s3})
);
wire [NUM_LANES-1:0] of_after_round;
@ -354,13 +354,13 @@ module VX_fpu_cvt #(
for (genvar i = 0; i < NUM_LANES; ++i) begin
// Detect special case from source format, I2F casts don't produce a special result
assign fp_result_is_special[i] = ~is_itof_s3 & (fp_clss_s3[i].is_zero | fp_clss_s3[i].is_nan);
assign fp_result_is_special[i] = ~is_itof_s3 & (fclass_s3[i].is_zero | fclass_s3[i].is_nan);
// Signalling input NaNs raise invalid flag, otherwise no flags set
assign fp_special_status[i] = fp_clss_s3[i].is_signaling ? {1'b1, 4'h0} : 5'h0; // invalid operation
assign fp_special_status[i] = fclass_s3[i].is_signaling ? {1'b1, 4'h0} : 5'h0; // invalid operation
// Assemble result according to destination format
assign fp_special_result[i] = fp_clss_s3[i].is_zero ? (32'(input_sign_s3) << 31) // signed zero
assign fp_special_result[i] = fclass_s3[i].is_zero ? (32'(input_sign_s3) << 31) // signed zero
: {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN
end
@ -373,7 +373,7 @@ module VX_fpu_cvt #(
for (genvar i = 0; i < NUM_LANES; ++i) begin
// Assemble result according to destination format
always @(*) begin
if (input_sign_s3[i] && !fp_clss_s3[i].is_nan) begin
if (input_sign_s3[i] && !fclass_s3[i].is_nan) begin
int_special_result[i][30:0] = '0; // alone yields 2**(31)-1
int_special_result[i][31] = ~unsigned_s3; // for unsigned casts yields 2**31
end else begin
@ -383,8 +383,8 @@ module VX_fpu_cvt #(
end
// Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned)
assign int_result_is_special[i] = fp_clss_s3[i].is_nan
| fp_clss_s3[i].is_inf
assign int_result_is_special[i] = fclass_s3[i].is_nan
| fclass_s3[i].is_inf
| of_before_round_s3[i]
| (input_sign_s3[i] & unsigned_s3 & ~rounded_int_res_zero[i]);
@ -403,11 +403,11 @@ module VX_fpu_cvt #(
wire [31:0] fp_result, int_result;
wire inexact = is_itof_s3 ? (| fp_round_sticky_bits[i]) // overflow is invalid in i2f;
: (| fp_round_sticky_bits[i]) | (~fp_clss_s3[i].is_inf & (of_before_round_s3[i] | of_after_round[i]));
: (| fp_round_sticky_bits[i]) | (~fclass_s3[i].is_inf & (of_before_round_s3[i] | of_after_round[i]));
assign fp_regular_status.NV = is_itof_s3 & (of_before_round_s3[i] | of_after_round[i]); // overflow is invalid for I2F casts
assign fp_regular_status.DZ = 1'b0; // no divisions
assign fp_regular_status.OF = ~is_itof_s3 & (~fp_clss_s3[i].is_inf & (of_before_round_s3[i] | of_after_round[i])); // inf casts no OF
assign fp_regular_status.OF = ~is_itof_s3 & (~fclass_s3[i].is_inf & (of_before_round_s3[i] | of_after_round[i])); // inf casts no OF
assign fp_regular_status.UF = uf_after_round[i] & inexact;
assign fp_regular_status.NX = inexact;
@ -427,7 +427,7 @@ module VX_fpu_cvt #(
assign stall = ~ready_out && valid_out;
VX_pipe_register #(
.DATAW (1 + TAGW + (NUM_LANES * 32) + (NUM_LANES * `FFLAGS_BITS)),
.DATAW (1 + TAGW + (NUM_LANES * 32) + (NUM_LANES * `FP_FLAGS_BITS)),
.RESETW (1)
) pipe_reg4 (
.clk (clk),

54
hw/rtl/fpu_unit/VX_fpu_ncomp.sv
View file

@ -47,7 +47,7 @@ module VX_fpu_ncomp #(
wire [NUM_LANES-1:0] a_sign, b_sign;
wire [NUM_LANES-1:0][7:0] a_exponent, b_exponent;
wire [NUM_LANES-1:0][22:0] a_mantissa, b_mantissa;
fp_class_t [NUM_LANES-1:0] a_clss, b_clss;
fclass_t [NUM_LANES-1:0] a_fclass, b_fclass;
wire [NUM_LANES-1:0] a_smaller, ab_equal;
// Setup
@ -66,7 +66,7 @@ module VX_fpu_ncomp #(
) fp_class_a (
.exp_i (a_exponent[i]),
.man_i (a_mantissa[i]),
.clss_o (a_clss[i])
.clss_o (a_fclass[i])
);
VX_fpu_class #(
@ -75,58 +75,58 @@ module VX_fpu_ncomp #(
) fp_class_b (
.exp_i (b_exponent[i]),
.man_i (b_mantissa[i]),
.clss_o (b_clss[i])
.clss_o (b_fclass[i])
);
assign a_smaller[i] = $signed(dataa[i]) < $signed(datab[i]);
assign ab_equal[i] = (dataa[i] == datab[i]) | (a_clss[i].is_zero & b_clss[i].is_zero);
assign ab_equal[i] = (dataa[i] == datab[i]) | (a_fclass[i].is_zero & b_fclass[i].is_zero);
end
// Pipeline stage0
wire valid_in_s0;
wire [TAGW-1:0] tag_in_s0;
wire [`INST_FPU_BITS-1:0] op_type_s0;
wire [`INST_FRM_BITS-1:0] frm_s0;
wire valid_in_s0;
wire [TAGW-1:0] tag_in_s0;
wire [`INST_FPU_BITS-1:0] op_type_s0;
wire [`INST_FRM_BITS-1:0] frm_s0;
wire [NUM_LANES-1:0][31:0] dataa_s0, datab_s0;
wire [NUM_LANES-1:0] a_sign_s0, b_sign_s0;
wire [NUM_LANES-1:0][7:0] a_exponent_s0;
wire [NUM_LANES-1:0][22:0] a_mantissa_s0;
fp_class_t [NUM_LANES-1:0] a_clss_s0, b_clss_s0;
fclass_t [NUM_LANES-1:0] a_fclass_s0, b_fclass_s0;
wire [NUM_LANES-1:0] a_smaller_s0, ab_equal_s0;
wire stall;
VX_pipe_register #(
.DATAW (1 + TAGW + `INST_FPU_BITS + `INST_FRM_BITS + NUM_LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fp_class_t) + 1 + 1)),
.DATAW (1 + TAGW + `INST_FPU_BITS + `INST_FRM_BITS + NUM_LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fclass_t) + 1 + 1)),
.RESETW (1),
.DEPTH (0)
) pipe_reg0 (
.clk (clk),
.reset (reset),
.enable (!stall),
.data_in ({valid_in, tag_in, op_type, frm, dataa, datab, a_sign, b_sign, a_exponent, a_mantissa, a_clss, b_clss, a_smaller, ab_equal}),
.data_out ({valid_in_s0, tag_in_s0, op_type_s0, frm_s0, dataa_s0, datab_s0, a_sign_s0, b_sign_s0, a_exponent_s0, a_mantissa_s0, a_clss_s0, b_clss_s0, a_smaller_s0, ab_equal_s0})
.data_in ({valid_in, tag_in, op_type, frm, dataa, datab, a_sign, b_sign, a_exponent, a_mantissa, a_fclass, b_fclass, a_smaller, ab_equal}),
.data_out ({valid_in_s0, tag_in_s0, op_type_s0, frm_s0, dataa_s0, datab_s0, a_sign_s0, b_sign_s0, a_exponent_s0, a_mantissa_s0, a_fclass_s0, b_fclass_s0, a_smaller_s0, ab_equal_s0})
);
// FCLASS
reg [NUM_LANES-1:0][31:0] fclass_mask; // generate a 10-bit mask for integer reg
for (genvar i = 0; i < NUM_LANES; ++i) begin
always @(*) begin
if (a_clss_s0[i].is_normal) begin
if (a_fclass_s0[i].is_normal) begin
fclass_mask[i] = a_sign_s0[i] ? NEG_NORM : POS_NORM;
end
else if (a_clss_s0[i].is_inf) begin
else if (a_fclass_s0[i].is_inf) begin
fclass_mask[i] = a_sign_s0[i] ? NEG_INF : POS_INF;
end
else if (a_clss_s0[i].is_zero) begin
else if (a_fclass_s0[i].is_zero) begin
fclass_mask[i] = a_sign_s0[i] ? NEG_ZERO : POS_ZERO;
end
else if (a_clss_s0[i].is_subnormal) begin
else if (a_fclass_s0[i].is_subnormal) begin
fclass_mask[i] = a_sign_s0[i] ? NEG_SUBNORM : POS_SUBNORM;
end
else if (a_clss_s0[i].is_nan) begin
fclass_mask[i] = {22'h0, a_clss_s0[i].is_quiet, a_clss_s0[i].is_signaling, 8'h0};
else if (a_fclass_s0[i].is_nan) begin
fclass_mask[i] = {22'h0, a_fclass_s0[i].is_quiet, a_fclass_s0[i].is_signaling, 8'h0};
end
else begin
fclass_mask[i] = QUT_NAN;
@ -138,11 +138,11 @@ module VX_fpu_ncomp #(
reg [NUM_LANES-1:0][31:0] fminmax_res; // result of fmin/fmax
for (genvar i = 0; i < NUM_LANES; ++i) begin
always @(*) begin
if (a_clss_s0[i].is_nan && b_clss_s0[i].is_nan)
if (a_fclass_s0[i].is_nan && b_fclass_s0[i].is_nan)
fminmax_res[i] = {1'b0, 8'hff, 1'b1, 22'd0}; // canonical qNaN
else if (a_clss_s0[i].is_nan)
else if (a_fclass_s0[i].is_nan)
fminmax_res[i] = datab_s0[i];
else if (b_clss_s0[i].is_nan)
else if (b_fclass_s0[i].is_nan)
fminmax_res[i] = dataa_s0[i];
else begin
case (frm_s0) // use LSB to distinguish MIN and MAX
@ -175,7 +175,7 @@ module VX_fpu_ncomp #(
case (frm_s0)
`INST_FRM_RNE: begin // LE
fcmp_fflags[i] = 5'h0;
if (a_clss_s0[i].is_nan || b_clss_s0[i].is_nan) begin
if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
fcmp_res[i] = 32'h0;
fcmp_fflags[i].NV = 1'b1;
end else begin
@ -184,7 +184,7 @@ module VX_fpu_ncomp #(
end
`INST_FRM_RTZ: begin // LS
fcmp_fflags[i] = 5'h0;
if (a_clss_s0[i].is_nan || b_clss_s0[i].is_nan) begin
if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
fcmp_res[i] = 32'h0;
fcmp_fflags[i].NV = 1'b1;
end else begin
@ -193,9 +193,9 @@ module VX_fpu_ncomp #(
end
`INST_FRM_RDN: begin // EQ
fcmp_fflags[i] = 5'h0;
if (a_clss_s0[i].is_nan || b_clss_s0[i].is_nan) begin
if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
fcmp_res[i] = 32'h0;
fcmp_fflags[i].NV = a_clss_s0[i].is_signaling | b_clss_s0[i].is_signaling;
fcmp_fflags[i].NV = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling;
end else begin
fcmp_res[i] = {31'h0, ab_equal_s0[i]};
end
@ -234,7 +234,7 @@ module VX_fpu_ncomp #(
3,4: begin
tmp_result[i] = fminmax_res[i];
tmp_fflags[i] = 0;
tmp_fflags[i].NV = a_clss_s0[i].is_signaling | b_clss_s0[i].is_signaling;
tmp_fflags[i].NV = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling;
end
//5,6,7: MOVE
default: begin
@ -255,7 +255,7 @@ module VX_fpu_ncomp #(
assign stall = ~ready_out && valid_out;
VX_pipe_register #(
.DATAW (1 + TAGW + (NUM_LANES * 32) + 1 + (NUM_LANES * `FFLAGS_BITS)),
.DATAW (1 + TAGW + (NUM_LANES * 32) + 1 + (NUM_LANES * `FP_FLAGS_BITS)),
.RESETW (1)
) pipe_reg1 (
.clk (clk),

6
hw/rtl/fpu_unit/VX_fpu_types.vh
View file

@ -13,7 +13,7 @@ typedef struct packed {
logic is_nan;
logic is_quiet;
logic is_signaling;
} fp_class_t;
} fclass_t;
typedef struct packed {
logic NV; // 4-Invalid
@ -25,7 +25,7 @@ typedef struct packed {
endpackage
`define FP_CLASS_BITS $bits(VX_fpu_types::fp_class_t)
`define FFLAGS_BITS $bits(VX_fpu_types::fflags_t)
`define FP_CLASS_BITS $bits(VX_fpu_types::fclass_t)
`define FP_FLAGS_BITS $bits(VX_fpu_types::fflags_t)
`endif