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test memory bank interleaving

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This commit is contained in:
Blaise Tine 2024-09-23 04:30:28 -07:00
parent e5e9a5c2e9
commit 030071571d
2 changed files with 9 additions and 1 deletions
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4
ci/regression.sh.in
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@ -285,6 +285,10 @@ config2()
CONFIGS="-DPLATFORM_MEMORY_ADDR_WIDTH=33" ./ci/blackbox.sh --driver=opae --app=mstress
CONFIGS="-DPLATFORM_MEMORY_ADDR_WIDTH=33" ./ci/blackbox.sh --driver=xrt --app=mstress
# test DRAM banks interleaving
CONFIGS="-DPLATFORM_MEMORY_INTERLEAVE=1" ./ci/blackbox.sh --driver=opae --app=mstress
CONFIGS="-DPLATFORM_MEMORY_INTERLEAVE=0" ./ci/blackbox.sh --driver=opae --app=mstress
echo "configuration-2 tests done!"
}

6
hw/rtl/afu/opae/vortex_afu.sv
View file

@ -18,6 +18,10 @@
`endif
`include "VX_define.vh"
`ifndef PLATFORM_MEMORY_INTERLEAVE
`define PLATFORM_MEMORY_INTERLEAVE 1
`endif
module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_gpu_pkg::*; #(
parameter NUM_LOCAL_MEM_BANKS = 2
) (
@ -604,7 +608,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
.TAG_WIDTH (AVS_REQ_TAGW + 1),
.RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE),
.AVS_ADDR_WIDTH($bits(t_local_mem_addr)),
.BANK_INTERLEAVE (1),
.BANK_INTERLEAVE (`PLATFORM_MEMORY_INTERLEAVE),
.REQ_OUT_BUF (2),
.RSP_OUT_BUF (0)
) avs_adapter (