github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-23 21:39:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Moved 64-bit riscv-tests to tests/riscv/isa from tests/riscv/isa64

Browse source
This commit is contained in:
Santosh Srivatsan 2021-12-13 20:21:51 -05:00
parent d14e05e748
commit 039f5eb733
90 changed files with 290 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

17
tests/riscv/isa/Makefile
View file

@ -1,16 +1,23 @@
ALL_TESTS := $(wildcard *.hex)
ALL_TESTS := $(wildcard *.hex)
ALL_TESTS_32 := $(wildcard rv32*.hex)
ALL_TESTS_64 := $(wildcard rv64*.hex)
D_TESTS := $(wildcard *ud-p-*.hex)
V_TESTS := $(wildcard *-v-*.hex)
EXCLUDED_TESTS := $(V_TESTS) $(D_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex
EXCLUDED_TESTS_32 := $(V_TESTS) $(D_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex
EXCLUDED_TESTS_64 := rv64ud-p-move.hex
TESTS := $(filter-out $(EXCLUDED_TESTS), $(ALL_TESTS))
TESTS_32 := $(filter-out $(EXCLUDED_TESTS_32), $(ALL_TESTS_32))
TESTS_64 := $(filter-out $(EXCLUDED_TESTS_64), $(ALL_TESTS_64))
all:
run-simx:
$(foreach test, $(TESTS), ../../../sim/simx/simx -r -a rv32i -c 1 -i $(test) || exit;)
run-simx-32:
$(foreach test, $(TESTS_32), ../../../sim/simx/simx -r -a rv32i -c 1 -i $(test) || exit;)
run-simx-64:
$(foreach test, $(TESTS_64), ../../../sim/simx/simx -r -a rv64imfd -c 1 -i $(test) || exit;)
run-rtlsim:
$(foreach test, $(TESTS), ../../../sim/rtlsim/rtlsim -r $(test) || exit;)

278
tests/riscv/isa/ramulator.ddr4.log Normal file
View file

@ -0,0 +1,278 @@
ramulator.active_cycles_0 76 # Total active cycles for level _0
ramulator.busy_cycles_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0
ramulator.serving_requests_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0
ramulator.average_serving_requests_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0
ramulator.active_cycles_0_0 76 # Total active cycles for level _0_0
ramulator.busy_cycles_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0
ramulator.serving_requests_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0
ramulator.average_serving_requests_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0
ramulator.active_cycles_0_0_0 76 # Total active cycles for level _0_0_0
ramulator.busy_cycles_0_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0
ramulator.serving_requests_0_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0
ramulator.average_serving_requests_0_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0
ramulator.active_cycles_0_0_0_0 76 # Total active cycles for level _0_0_0_0
ramulator.busy_cycles_0_0_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0
ramulator.serving_requests_0_0_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0
ramulator.average_serving_requests_0_0_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0
ramulator.active_cycles_0_0_0_1 0 # Total active cycles for level _0_0_0_1
ramulator.busy_cycles_0_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1
ramulator.serving_requests_0_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1
ramulator.average_serving_requests_0_0_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1
ramulator.active_cycles_0_0_0_2 0 # Total active cycles for level _0_0_0_2
ramulator.busy_cycles_0_0_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2
ramulator.serving_requests_0_0_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2
ramulator.average_serving_requests_0_0_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2
ramulator.active_cycles_0_0_0_3 0 # Total active cycles for level _0_0_0_3
ramulator.busy_cycles_0_0_0_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3
ramulator.serving_requests_0_0_0_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3
ramulator.average_serving_requests_0_0_0_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3
ramulator.active_cycles_0_0_1 0 # Total active cycles for level _0_0_1
ramulator.busy_cycles_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1
ramulator.serving_requests_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1
ramulator.average_serving_requests_0_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1
ramulator.active_cycles_0_0_1_0 0 # Total active cycles for level _0_0_1_0
ramulator.busy_cycles_0_0_1_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0
ramulator.serving_requests_0_0_1_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0
ramulator.average_serving_requests_0_0_1_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0
ramulator.active_cycles_0_0_1_1 0 # Total active cycles for level _0_0_1_1
ramulator.busy_cycles_0_0_1_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1
ramulator.serving_requests_0_0_1_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1
ramulator.average_serving_requests_0_0_1_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1
ramulator.active_cycles_0_0_1_2 0 # Total active cycles for level _0_0_1_2
ramulator.busy_cycles_0_0_1_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2
ramulator.serving_requests_0_0_1_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2
ramulator.average_serving_requests_0_0_1_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2
ramulator.active_cycles_0_0_1_3 0 # Total active cycles for level _0_0_1_3
ramulator.busy_cycles_0_0_1_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3
ramulator.serving_requests_0_0_1_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3
ramulator.average_serving_requests_0_0_1_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3
ramulator.active_cycles_0_0_2 0 # Total active cycles for level _0_0_2
ramulator.busy_cycles_0_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2
ramulator.serving_requests_0_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2
ramulator.average_serving_requests_0_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2
ramulator.active_cycles_0_0_2_0 0 # Total active cycles for level _0_0_2_0
ramulator.busy_cycles_0_0_2_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0
ramulator.serving_requests_0_0_2_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0
ramulator.average_serving_requests_0_0_2_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0
ramulator.active_cycles_0_0_2_1 0 # Total active cycles for level _0_0_2_1
ramulator.busy_cycles_0_0_2_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1
ramulator.serving_requests_0_0_2_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1
ramulator.average_serving_requests_0_0_2_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1
ramulator.active_cycles_0_0_2_2 0 # Total active cycles for level _0_0_2_2
ramulator.busy_cycles_0_0_2_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2
ramulator.serving_requests_0_0_2_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2
ramulator.average_serving_requests_0_0_2_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2
ramulator.active_cycles_0_0_2_3 0 # Total active cycles for level _0_0_2_3
ramulator.busy_cycles_0_0_2_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3
ramulator.serving_requests_0_0_2_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3
ramulator.average_serving_requests_0_0_2_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3
ramulator.active_cycles_0_0_3 0 # Total active cycles for level _0_0_3
ramulator.busy_cycles_0_0_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3
ramulator.serving_requests_0_0_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3
ramulator.average_serving_requests_0_0_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3
ramulator.active_cycles_0_0_3_0 0 # Total active cycles for level _0_0_3_0
ramulator.busy_cycles_0_0_3_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0
ramulator.serving_requests_0_0_3_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0
ramulator.average_serving_requests_0_0_3_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0
ramulator.active_cycles_0_0_3_1 0 # Total active cycles for level _0_0_3_1
ramulator.busy_cycles_0_0_3_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1
ramulator.serving_requests_0_0_3_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1
ramulator.average_serving_requests_0_0_3_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1
ramulator.active_cycles_0_0_3_2 0 # Total active cycles for level _0_0_3_2
ramulator.busy_cycles_0_0_3_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2
ramulator.serving_requests_0_0_3_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2
ramulator.average_serving_requests_0_0_3_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2
ramulator.active_cycles_0_0_3_3 0 # Total active cycles for level _0_0_3_3
ramulator.busy_cycles_0_0_3_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3
ramulator.serving_requests_0_0_3_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3
ramulator.average_serving_requests_0_0_3_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3
ramulator.read_transaction_bytes_0 192 # The total byte of read transaction per channel
ramulator.write_transaction_bytes_0 0 # The total byte of write transaction per channel
ramulator.row_hits_channel_0_core 2 # Number of row hits per channel per core
ramulator.row_misses_channel_0_core 1 # Number of row misses per channel per core
ramulator.row_conflicts_channel_0_core 0 # Number of row conflicts per channel per core
ramulator.read_row_hits_channel_0_core 2 # Number of row hits for read requests per channel per core
[0] 2.0 #
ramulator.read_row_misses_channel_0_core 1 # Number of row misses for read requests per channel per core
[0] 1.0 #
ramulator.read_row_conflicts_channel_0_core 0 # Number of row conflicts for read requests per channel per core
[0] 0.0 #
ramulator.write_row_hits_channel_0_core 0 # Number of row hits for write requests per channel per core
[0] 0.0 #
ramulator.write_row_misses_channel_0_core 0 # Number of row misses for write requests per channel per core
[0] 0.0 #
ramulator.write_row_conflicts_channel_0_core 0 # Number of row conflicts for write requests per channel per core
[0] 0.0 #
ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR
ramulator.read_latency_avg_0 26.333333 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel
ramulator.read_latency_sum_0 79 # The memory latency cycles (in memory time domain) sum for all read requests in this channel
ramulator.req_queue_length_avg_0 0.046529 # Average of read and write queue length per memory cycle per channel.
ramulator.req_queue_length_sum_0 63 # Sum of read and write queue length per memory cycle per channel.
ramulator.read_req_queue_length_avg_0 0.046529 # Read queue length average per memory cycle per channel.
ramulator.read_req_queue_length_sum_0 63 # Read queue length sum per memory cycle per channel.
ramulator.write_req_queue_length_avg_0 0.000000 # Write queue length average per memory cycle per channel.
ramulator.write_req_queue_length_sum_0 0 # Write queue length sum per memory cycle per channel.
ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.active_cycles_1 76 # Total active cycles for level _1
ramulator.busy_cycles_1 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1
ramulator.serving_requests_1 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1
ramulator.average_serving_requests_1 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1
ramulator.active_cycles_1_0 76 # Total active cycles for level _1_0
ramulator.busy_cycles_1_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0
ramulator.serving_requests_1_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0
ramulator.average_serving_requests_1_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0
ramulator.active_cycles_1_0_0 76 # Total active cycles for level _1_0_0
ramulator.busy_cycles_1_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0
ramulator.serving_requests_1_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0
ramulator.average_serving_requests_1_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0
ramulator.active_cycles_1_0_0_0 76 # Total active cycles for level _1_0_0_0
ramulator.busy_cycles_1_0_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_0
ramulator.serving_requests_1_0_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_0
ramulator.average_serving_requests_1_0_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_0
ramulator.active_cycles_1_0_0_1 0 # Total active cycles for level _1_0_0_1
ramulator.busy_cycles_1_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_1
ramulator.serving_requests_1_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_1
ramulator.average_serving_requests_1_0_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_1
ramulator.active_cycles_1_0_0_2 0 # Total active cycles for level _1_0_0_2
ramulator.busy_cycles_1_0_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_2
ramulator.serving_requests_1_0_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_2
ramulator.average_serving_requests_1_0_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_2
ramulator.active_cycles_1_0_0_3 0 # Total active cycles for level _1_0_0_3
ramulator.busy_cycles_1_0_0_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_3
ramulator.serving_requests_1_0_0_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_3
ramulator.average_serving_requests_1_0_0_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_3
ramulator.active_cycles_1_0_1 0 # Total active cycles for level _1_0_1
ramulator.busy_cycles_1_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1
ramulator.serving_requests_1_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1
ramulator.average_serving_requests_1_0_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1
ramulator.active_cycles_1_0_1_0 0 # Total active cycles for level _1_0_1_0
ramulator.busy_cycles_1_0_1_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_0
ramulator.serving_requests_1_0_1_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_0
ramulator.average_serving_requests_1_0_1_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_0
ramulator.active_cycles_1_0_1_1 0 # Total active cycles for level _1_0_1_1
ramulator.busy_cycles_1_0_1_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_1
ramulator.serving_requests_1_0_1_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_1
ramulator.average_serving_requests_1_0_1_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_1
ramulator.active_cycles_1_0_1_2 0 # Total active cycles for level _1_0_1_2
ramulator.busy_cycles_1_0_1_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_2
ramulator.serving_requests_1_0_1_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_2
ramulator.average_serving_requests_1_0_1_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_2
ramulator.active_cycles_1_0_1_3 0 # Total active cycles for level _1_0_1_3
ramulator.busy_cycles_1_0_1_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_1_3
ramulator.serving_requests_1_0_1_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_3
ramulator.average_serving_requests_1_0_1_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_1_3
ramulator.active_cycles_1_0_2 0 # Total active cycles for level _1_0_2
ramulator.busy_cycles_1_0_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2
ramulator.serving_requests_1_0_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2
ramulator.average_serving_requests_1_0_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2
ramulator.active_cycles_1_0_2_0 0 # Total active cycles for level _1_0_2_0
ramulator.busy_cycles_1_0_2_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_0
ramulator.serving_requests_1_0_2_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_0
ramulator.average_serving_requests_1_0_2_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_0
ramulator.active_cycles_1_0_2_1 0 # Total active cycles for level _1_0_2_1
ramulator.busy_cycles_1_0_2_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_1
ramulator.serving_requests_1_0_2_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_1
ramulator.average_serving_requests_1_0_2_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_1
ramulator.active_cycles_1_0_2_2 0 # Total active cycles for level _1_0_2_2
ramulator.busy_cycles_1_0_2_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_2
ramulator.serving_requests_1_0_2_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_2
ramulator.average_serving_requests_1_0_2_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_2
ramulator.active_cycles_1_0_2_3 0 # Total active cycles for level _1_0_2_3
ramulator.busy_cycles_1_0_2_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_2_3
ramulator.serving_requests_1_0_2_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_3
ramulator.average_serving_requests_1_0_2_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_2_3
ramulator.active_cycles_1_0_3 0 # Total active cycles for level _1_0_3
ramulator.busy_cycles_1_0_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3
ramulator.serving_requests_1_0_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3
ramulator.average_serving_requests_1_0_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3
ramulator.active_cycles_1_0_3_0 0 # Total active cycles for level _1_0_3_0
ramulator.busy_cycles_1_0_3_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_0
ramulator.serving_requests_1_0_3_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_0
ramulator.average_serving_requests_1_0_3_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_0
ramulator.active_cycles_1_0_3_1 0 # Total active cycles for level _1_0_3_1
ramulator.busy_cycles_1_0_3_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_1
ramulator.serving_requests_1_0_3_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_1
ramulator.average_serving_requests_1_0_3_1 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_1
ramulator.active_cycles_1_0_3_2 0 # Total active cycles for level _1_0_3_2
ramulator.busy_cycles_1_0_3_2 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_2
ramulator.serving_requests_1_0_3_2 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_2
ramulator.average_serving_requests_1_0_3_2 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_2
ramulator.active_cycles_1_0_3_3 0 # Total active cycles for level _1_0_3_3
ramulator.busy_cycles_1_0_3_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_3_3
ramulator.serving_requests_1_0_3_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_3
ramulator.average_serving_requests_1_0_3_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_3_3
ramulator.read_transaction_bytes_1 192 # The total byte of read transaction per channel
ramulator.write_transaction_bytes_1 0 # The total byte of write transaction per channel
ramulator.row_hits_channel_1_core 2 # Number of row hits per channel per core
ramulator.row_misses_channel_1_core 1 # Number of row misses per channel per core
ramulator.row_conflicts_channel_1_core 0 # Number of row conflicts per channel per core
ramulator.read_row_hits_channel_1_core 2 # Number of row hits for read requests per channel per core
[0] 2.0 #
ramulator.read_row_misses_channel_1_core 1 # Number of row misses for read requests per channel per core
[0] 1.0 #
ramulator.read_row_conflicts_channel_1_core 0 # Number of row conflicts for read requests per channel per core
[0] 0.0 #
ramulator.write_row_hits_channel_1_core 0 # Number of row hits for write requests per channel per core
[0] 0.0 #
ramulator.write_row_misses_channel_1_core 0 # Number of row misses for write requests per channel per core
[0] 0.0 #
ramulator.write_row_conflicts_channel_1_core 0 # Number of row conflicts for write requests per channel per core
[0] 0.0 #
ramulator.useless_activates_1_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR
ramulator.read_latency_avg_1 26.333333 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel
ramulator.read_latency_sum_1 79 # The memory latency cycles (in memory time domain) sum for all read requests in this channel
ramulator.req_queue_length_avg_1 0.046529 # Average of read and write queue length per memory cycle per channel.
ramulator.req_queue_length_sum_1 63 # Sum of read and write queue length per memory cycle per channel.
ramulator.read_req_queue_length_avg_1 0.046529 # Read queue length average per memory cycle per channel.
ramulator.read_req_queue_length_sum_1 63 # Read queue length sum per memory cycle per channel.
ramulator.write_req_queue_length_avg_1 0.000000 # Write queue length average per memory cycle per channel.
ramulator.write_req_queue_length_sum_1 0 # Write queue length sum per memory cycle per channel.
ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM
ramulator.dram_cycles 1354 # Number of DRAM cycles simulated
ramulator.incoming_requests 6 # Number of incoming requests to DRAM
ramulator.read_requests 6 # Number of incoming read requests to DRAM per core
[0] 6.0 #
ramulator.write_requests 0 # Number of incoming write requests to DRAM per core
[0] 0.0 #
ramulator.ramulator_active_cycles 152 # The total number of cycles that the DRAM part is active (serving R/W)
ramulator.incoming_requests_per_channel 6.0 # Number of incoming requests to each DRAM channel
[0] 3.0 #
[1] 3.0 #
ramulator.incoming_read_reqs_per_channel 6.0 # Number of incoming read requests to each DRAM channel
[0] 3.0 #
[1] 3.0 #
ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens.
ramulator.maximum_bandwidth 38400000000 # The theoretical maximum bandwidth (Bps)
ramulator.in_queue_req_num_sum 126 # Sum of read/write queue length
ramulator.in_queue_read_req_num_sum 126 # Sum of read queue length
ramulator.in_queue_write_req_num_sum 0 # Sum of write queue length
ramulator.in_queue_req_num_avg 0.093058 # Average of read/write queue length per memory cycle
ramulator.in_queue_read_req_num_avg 0.093058 # Average of read queue length per memory cycle
ramulator.in_queue_write_req_num_avg 0.000000 # Average of write queue length per memory cycle
ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end
[0] 0.0 #
ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end
[0] 0.0 #

0
tests/riscv/isa64/rv64ud-p-fadd.hex → tests/riscv/isa/rv64ud-p-fadd.hex
View file

0
tests/riscv/isa64/rv64ud-p-fclass.hex → tests/riscv/isa/rv64ud-p-fclass.hex
View file

0
tests/riscv/isa64/rv64ud-p-fcmp.hex → tests/riscv/isa/rv64ud-p-fcmp.hex
View file

0
tests/riscv/isa64/rv64ud-p-fcvt.hex → tests/riscv/isa/rv64ud-p-fcvt.hex
View file

0
tests/riscv/isa64/rv64ud-p-fcvt_w.hex → tests/riscv/isa/rv64ud-p-fcvt_w.hex
View file

0
tests/riscv/isa64/rv64ud-p-fdiv.hex → tests/riscv/isa/rv64ud-p-fdiv.hex
View file

0
tests/riscv/isa64/rv64ud-p-fmadd.hex → tests/riscv/isa/rv64ud-p-fmadd.hex
View file

0
tests/riscv/isa64/rv64ud-p-fmin.hex → tests/riscv/isa/rv64ud-p-fmin.hex
View file

0
tests/riscv/isa64/rv64ud-p-ldst.hex → tests/riscv/isa/rv64ud-p-ldst.hex
View file

0
tests/riscv/isa64/rv64ud-p-move.hex → tests/riscv/isa/rv64ud-p-move.hex
View file

0
tests/riscv/isa64/rv64ud-p-recoding.hex → tests/riscv/isa/rv64ud-p-recoding.hex
View file

0
tests/riscv/isa64/rv64ud-p-structural.hex → tests/riscv/isa/rv64ud-p-structural.hex
View file

0
tests/riscv/isa64/rv64uf-p-fadd.hex → tests/riscv/isa/rv64uf-p-fadd.hex
View file

0
tests/riscv/isa64/rv64uf-p-fclass.hex → tests/riscv/isa/rv64uf-p-fclass.hex
View file

0
tests/riscv/isa64/rv64uf-p-fcmp.hex → tests/riscv/isa/rv64uf-p-fcmp.hex
View file

0
tests/riscv/isa64/rv64uf-p-fcvt.hex → tests/riscv/isa/rv64uf-p-fcvt.hex
View file

0
tests/riscv/isa64/rv64uf-p-fcvt_w.hex → tests/riscv/isa/rv64uf-p-fcvt_w.hex
View file

0
tests/riscv/isa64/rv64uf-p-fdiv.hex → tests/riscv/isa/rv64uf-p-fdiv.hex
View file

0
tests/riscv/isa64/rv64uf-p-fmadd.hex → tests/riscv/isa/rv64uf-p-fmadd.hex
View file

0
tests/riscv/isa64/rv64uf-p-fmin.hex → tests/riscv/isa/rv64uf-p-fmin.hex
View file

0
tests/riscv/isa64/rv64uf-p-ldst.hex → tests/riscv/isa/rv64uf-p-ldst.hex
View file

0
tests/riscv/isa64/rv64uf-p-move.hex → tests/riscv/isa/rv64uf-p-move.hex
View file

0
tests/riscv/isa64/rv64uf-p-recoding.hex → tests/riscv/isa/rv64uf-p-recoding.hex
View file

0
tests/riscv/isa64/rv64ui-p-add.hex → tests/riscv/isa/rv64ui-p-add.hex
View file

0
tests/riscv/isa64/rv64ui-p-addi.hex → tests/riscv/isa/rv64ui-p-addi.hex
View file

0
tests/riscv/isa64/rv64ui-p-addiw.hex → tests/riscv/isa/rv64ui-p-addiw.hex
View file

0
tests/riscv/isa64/rv64ui-p-addw.hex → tests/riscv/isa/rv64ui-p-addw.hex
View file

0
tests/riscv/isa64/rv64ui-p-and.hex → tests/riscv/isa/rv64ui-p-and.hex
View file

0
tests/riscv/isa64/rv64ui-p-andi.hex → tests/riscv/isa/rv64ui-p-andi.hex
View file

0
tests/riscv/isa64/rv64ui-p-auipc.hex → tests/riscv/isa/rv64ui-p-auipc.hex
View file

0
tests/riscv/isa64/rv64ui-p-beq.hex → tests/riscv/isa/rv64ui-p-beq.hex
View file

0
tests/riscv/isa64/rv64ui-p-bge.hex → tests/riscv/isa/rv64ui-p-bge.hex
View file

0
tests/riscv/isa64/rv64ui-p-bgeu.hex → tests/riscv/isa/rv64ui-p-bgeu.hex
View file

0
tests/riscv/isa64/rv64ui-p-blt.hex → tests/riscv/isa/rv64ui-p-blt.hex
View file

0
tests/riscv/isa64/rv64ui-p-bltu.hex → tests/riscv/isa/rv64ui-p-bltu.hex
View file

0
tests/riscv/isa64/rv64ui-p-bne.hex → tests/riscv/isa/rv64ui-p-bne.hex
View file

0
tests/riscv/isa64/rv64ui-p-fence_i.hex → tests/riscv/isa/rv64ui-p-fence_i.hex
View file

0
tests/riscv/isa64/rv64ui-p-jal.hex → tests/riscv/isa/rv64ui-p-jal.hex
View file

0
tests/riscv/isa64/rv64ui-p-jalr.hex → tests/riscv/isa/rv64ui-p-jalr.hex
View file

0
tests/riscv/isa64/rv64ui-p-lb.hex → tests/riscv/isa/rv64ui-p-lb.hex
View file

0
tests/riscv/isa64/rv64ui-p-lbu.hex → tests/riscv/isa/rv64ui-p-lbu.hex
View file

0
tests/riscv/isa64/rv64ui-p-ld.hex → tests/riscv/isa/rv64ui-p-ld.hex
View file

0
tests/riscv/isa64/rv64ui-p-lh.hex → tests/riscv/isa/rv64ui-p-lh.hex
View file

0
tests/riscv/isa64/rv64ui-p-lhu.hex → tests/riscv/isa/rv64ui-p-lhu.hex
View file

0
tests/riscv/isa64/rv64ui-p-lui.hex → tests/riscv/isa/rv64ui-p-lui.hex
View file

0
tests/riscv/isa64/rv64ui-p-lw.hex → tests/riscv/isa/rv64ui-p-lw.hex
View file

0
tests/riscv/isa64/rv64ui-p-lwu.hex → tests/riscv/isa/rv64ui-p-lwu.hex
View file

0
tests/riscv/isa64/rv64ui-p-or.hex → tests/riscv/isa/rv64ui-p-or.hex
View file

0
tests/riscv/isa64/rv64ui-p-ori.hex → tests/riscv/isa/rv64ui-p-ori.hex
View file

0
tests/riscv/isa64/rv64ui-p-sb.hex → tests/riscv/isa/rv64ui-p-sb.hex
View file

0
tests/riscv/isa64/rv64ui-p-sd.hex → tests/riscv/isa/rv64ui-p-sd.hex
View file

0
tests/riscv/isa64/rv64ui-p-sh.hex → tests/riscv/isa/rv64ui-p-sh.hex
View file

0
tests/riscv/isa64/rv64ui-p-simple.hex → tests/riscv/isa/rv64ui-p-simple.hex
View file

0
tests/riscv/isa64/rv64ui-p-sll.hex → tests/riscv/isa/rv64ui-p-sll.hex
View file

0
tests/riscv/isa64/rv64ui-p-slli.hex → tests/riscv/isa/rv64ui-p-slli.hex
View file

0
tests/riscv/isa64/rv64ui-p-slliw.hex → tests/riscv/isa/rv64ui-p-slliw.hex
View file

0
tests/riscv/isa64/rv64ui-p-sllw.hex → tests/riscv/isa/rv64ui-p-sllw.hex
View file

0
tests/riscv/isa64/rv64ui-p-slt.hex → tests/riscv/isa/rv64ui-p-slt.hex
View file

0
tests/riscv/isa64/rv64ui-p-slti.hex → tests/riscv/isa/rv64ui-p-slti.hex
View file

0
tests/riscv/isa64/rv64ui-p-sltiu.hex → tests/riscv/isa/rv64ui-p-sltiu.hex
View file

0
tests/riscv/isa64/rv64ui-p-sltu.hex → tests/riscv/isa/rv64ui-p-sltu.hex
View file

0
tests/riscv/isa64/rv64ui-p-sra.hex → tests/riscv/isa/rv64ui-p-sra.hex
View file

0
tests/riscv/isa64/rv64ui-p-srai.hex → tests/riscv/isa/rv64ui-p-srai.hex
View file

0
tests/riscv/isa64/rv64ui-p-sraiw.hex → tests/riscv/isa/rv64ui-p-sraiw.hex
View file

0
tests/riscv/isa64/rv64ui-p-sraw.hex → tests/riscv/isa/rv64ui-p-sraw.hex
View file

0
tests/riscv/isa64/rv64ui-p-srl.hex → tests/riscv/isa/rv64ui-p-srl.hex
View file

0
tests/riscv/isa64/rv64ui-p-srli.hex → tests/riscv/isa/rv64ui-p-srli.hex
View file

0
tests/riscv/isa64/rv64ui-p-srliw.hex → tests/riscv/isa/rv64ui-p-srliw.hex
View file

0
tests/riscv/isa64/rv64ui-p-srlw.hex → tests/riscv/isa/rv64ui-p-srlw.hex
View file

0
tests/riscv/isa64/rv64ui-p-sub.hex → tests/riscv/isa/rv64ui-p-sub.hex
View file

0
tests/riscv/isa64/rv64ui-p-subw.hex → tests/riscv/isa/rv64ui-p-subw.hex
View file

0
tests/riscv/isa64/rv64ui-p-sw.hex → tests/riscv/isa/rv64ui-p-sw.hex
View file

0
tests/riscv/isa64/rv64ui-p-xor.hex → tests/riscv/isa/rv64ui-p-xor.hex
View file

0
tests/riscv/isa64/rv64ui-p-xori.hex → tests/riscv/isa/rv64ui-p-xori.hex
View file

0
tests/riscv/isa64/rv64um-p-div.hex → tests/riscv/isa/rv64um-p-div.hex
View file

0
tests/riscv/isa64/rv64um-p-divu.hex → tests/riscv/isa/rv64um-p-divu.hex
View file

0
tests/riscv/isa64/rv64um-p-divuw.hex → tests/riscv/isa/rv64um-p-divuw.hex
View file

0
tests/riscv/isa64/rv64um-p-divw.hex → tests/riscv/isa/rv64um-p-divw.hex
View file

0
tests/riscv/isa64/rv64um-p-mul.hex → tests/riscv/isa/rv64um-p-mul.hex
View file

0
tests/riscv/isa64/rv64um-p-mulh.hex → tests/riscv/isa/rv64um-p-mulh.hex
View file

0
tests/riscv/isa64/rv64um-p-mulhsu.hex → tests/riscv/isa/rv64um-p-mulhsu.hex
View file

0
tests/riscv/isa64/rv64um-p-mulhu.hex → tests/riscv/isa/rv64um-p-mulhu.hex
View file

0
tests/riscv/isa64/rv64um-p-mulw.hex → tests/riscv/isa/rv64um-p-mulw.hex
View file

0
tests/riscv/isa64/rv64um-p-rem.hex → tests/riscv/isa/rv64um-p-rem.hex
View file

0
tests/riscv/isa64/rv64um-p-remu.hex → tests/riscv/isa/rv64um-p-remu.hex
View file

0
tests/riscv/isa64/rv64um-p-remuw.hex → tests/riscv/isa/rv64um-p-remuw.hex
View file

0
tests/riscv/isa64/rv64um-p-remw.hex → tests/riscv/isa/rv64um-p-remw.hex
View file

32
tests/riscv/isa64/Makefile
View file

@ -1,32 +0,0 @@
ALL_TESTS := $(wildcard *.hex)
EXCLUDED_TESTS := rv64ud-p-move.hex
I_TESTS := $(wildcard *ui-p-*.hex)
M_TESTS := $(wildcard *um-p-*.hex)
F_TESTS := $(wildcard *uf-p-*.hex)
D_TESTS := $(filter-out $(EXCLUDED_TESTS), $(wildcard *ud-p-*.hex))
TESTS := $(I_TESTS) $(M_TESTS) $(F_TESTS) $(D_TESTS)
all:
run-simx-i:
$(foreach test, $(I_TESTS), ../../../sim/simx/simx -r -a rv64i -c 1 -i $(test) || exit;)
run-simx-m:
$(foreach test, $(M_TESTS), ../../../sim/simx/simx -r -a rv64im -c 1 -i $(test) || exit;)
run-simx-f:
$(foreach test, $(F_TESTS), ../../../sim/simx/simx -r -a rv64imf -c 1 -i $(test) || exit;)
run-simx-d:
$(foreach test, $(D_TESTS), ../../../sim/simx/simx -r -a rv64imfd -c 1 -i $(test) || exit;)
run-simx:
$(foreach test, $(TESTS), ../../../sim/simx/simx -r -a rv64i -c 1 -i $(test) || exit;)
run-rtlsim:
$(foreach test, $(TESTS), ../../../sim/rtlsim/rtlsim -r $(test) || exit;)
clean: