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minor update

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This commit is contained in:
Blaise Tine 2024-03-30 05:33:57 -07:00
parent 6b81b26ffc
commit 03cf694238
20 changed files with 57 additions and 51 deletions
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1
hw/rtl/core/VX_fpu_unit.sv
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@ -11,7 +11,6 @@
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_define.vh"
`include "VX_fpu_define.vh"
module VX_fpu_unit import VX_fpu_pkg::*; #(

4
hw/rtl/fpu/VX_fcvt_unit.sv
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@ -14,10 +14,10 @@
// Modified port of cast module from fpnew Libray
// reference: https://github.com/pulp-platform/fpnew
`ifdef FPU_DSP
`include "VX_fpu_define.vh"
`ifdef FPU_DSP
module VX_fcvt_unit import VX_fpu_pkg::*; #(
parameter LATENCY = 1,
parameter INT_WIDTH = 32,

4
hw/rtl/fpu/VX_fncp_unit.sv
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@ -14,10 +14,10 @@
// Modified port of noncomp module from fpnew Libray
// reference: https://github.com/pulp-platform/fpnew
`ifdef FPU_DSP
`include "VX_fpu_define.vh"
`ifdef FPU_DSP
module VX_fncp_unit import VX_fpu_pkg::*; #(
parameter LATENCY = 2,
parameter EXP_BITS = 8,

4
hw/rtl/fpu/VX_fp_classifier.sv
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@ -11,10 +11,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
`ifdef FPU_DSP
`include "VX_fpu_define.vh"
`ifdef FPU_DSP
module VX_fp_classifier import VX_fpu_pkg::*; #(
parameter MAN_BITS = 23,
parameter EXP_BITS = 8

4
hw/rtl/fpu/VX_fp_rounding.sv
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@ -14,10 +14,10 @@
// Modified port of rouding module from fpnew Libray
// reference: https://github.com/pulp-platform/fpnew
`ifdef FPU_DSP
`include "VX_fpu_define.vh"
`ifdef FPU_DSP
module VX_fp_rounding #(
parameter DAT_WIDTH = 2 // Width of the abolute value, without sign bit
) (

0
hw/rtl/interfaces/VX_fpu_csr_if.sv → hw/rtl/fpu/VX_fpu_csr_if.sv
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4
hw/rtl/fpu/VX_fpu_cvt.sv
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@ -11,10 +11,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
`ifdef FPU_DSP
`include "VX_fpu_define.vh"
`ifdef FPU_DSP
module VX_fpu_cvt import VX_fpu_pkg::*; #(
parameter NUM_LANES = 5,
parameter NUM_PES = `UP(NUM_LANES / `FCVT_PE_RATIO),

4
hw/rtl/fpu/VX_fpu_div.sv
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@ -11,10 +11,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
`ifdef FPU_DSP
`include "VX_fpu_define.vh"
`ifdef FPU_DSP
module VX_fpu_div import VX_fpu_pkg::*; #(
parameter NUM_LANES = 1,
parameter NUM_PES = `UP(NUM_LANES / `FDIV_PE_RATIO),

4
hw/rtl/fpu/VX_fpu_dpi.sv
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@ -11,10 +11,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
`ifdef FPU_DPI
`include "VX_fpu_define.vh"
`ifdef FPU_DPI
module VX_fpu_dpi import VX_fpu_pkg::*; #(
parameter NUM_LANES = 1,
parameter TAG_WIDTH = 1,

4
hw/rtl/fpu/VX_fpu_dsp.sv
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@ -11,10 +11,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
`ifdef FPU_DSP
`include "VX_fpu_define.vh"
`ifdef FPU_DSP
module VX_fpu_dsp import VX_fpu_pkg::*; #(
parameter NUM_LANES = 4,
parameter TAG_WIDTH = 4,

4
hw/rtl/fpu/VX_fpu_fma.sv
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@ -11,10 +11,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
`ifdef FPU_DSP
`include "VX_fpu_define.vh"
`ifdef FPU_DSP
module VX_fpu_fma import VX_fpu_pkg::*; #(
parameter NUM_LANES = 1,
parameter NUM_PES = `UP(NUM_LANES / `FMA_PE_RATIO),

4
hw/rtl/fpu/VX_fpu_fpnew.sv
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@ -11,10 +11,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
`ifdef FPU_FPNEW
`include "VX_fpu_define.vh"
`ifdef FPU_FPNEW
module VX_fpu_fpnew
import VX_fpu_pkg::*;
import fpnew_pkg::*;

4
hw/rtl/fpu/VX_fpu_ncp.sv
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@ -11,10 +11,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
`ifdef FPU_DSP
`include "VX_fpu_define.vh"
`ifdef FPU_DSP
module VX_fpu_ncp import VX_fpu_pkg::*; #(
parameter NUM_LANES = 1,
parameter NUM_PES = `UP(NUM_LANES / `FNCP_PE_RATIO),

4
hw/rtl/fpu/VX_fpu_sqrt.sv
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@ -11,10 +11,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
`ifdef FPU_DSP
`include "VX_fpu_define.vh"
`ifdef FPU_DSP
module VX_fpu_sqrt import VX_fpu_pkg::*; #(
parameter NUM_LANES = 1,
parameter NUM_PES = `UP(NUM_LANES /`FSQRT_PE_RATIO),

0
hw/syn/altera/ip_gen.sh → hw/scripts/ip_gen.sh
View file

1
hw/syn/altera/common.mk
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@ -1 +0,0 @@
include ../common.mk

27
hw/syn/altera/opae/Makefile
View file

@ -7,14 +7,17 @@ PREFIX ?= build$(XLEN)
TARGET ?= fpga
NUM_CORES ?= 1
SCRIPT_DIR = ../../../scripts
RTL_DIR = ../../../rtl
DPI_DIR = ../../../dpi
AFU_DIR = $(RTL_DIR)/afu/opae
THIRD_PARTY_DIR = ../../../../third_party
IP_CACHE_DIR = ../ip_cache/$(DEVICE_FAMILY)
SRC_DIR := $(VORTEX_HOME)/hw/syn/altera/opae
BUILD_DIR = $(PREFIX)_$(DEVICE_FAMILY)_$(TARGET)_$(NUM_CORES)c
RTL_DIR := $(VORTEX_HOME)/hw/rtl
DPI_DIR := $(VORTEX_HOME)/hw/dpi
AFU_DIR := $(RTL_DIR)/afu/opae
THIRD_PARTY_DIR := $(VORTEX_HOME)/third_party
SCRIPT_DIR := $(VORTEX_HOME)/hw/scripts
IP_CACHE_DIR := $(ROOT_DIR)/hw/syn/altera/ip_cache/$(DEVICE_FAMILY)
BUILD_DIR := $(PREFIX)_$(DEVICE_FAMILY)_$(TARGET)_$(NUM_CORES)c
ifeq ($(shell which qsub-synth),)
RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 &
@ -100,20 +103,20 @@ all: swconfig ip-gen setup build
ip-gen: $(IP_CACHE_DIR)/ip-gen.log
$(IP_CACHE_DIR)/ip-gen.log:
../ip_gen.sh $(IP_CACHE_DIR)
$(SCRIPT_DIR)/ip_gen.sh $(IP_CACHE_DIR)
swconfig: vortex_afu.h
vortex_afu.h: vortex_afu.json
vortex_afu.h: $(SRC_DIR)/vortex_afu.json
afu_json_mgr json-info --afu-json=$^ --c-hdr=$@
$(BUILD_DIR)/setup.cfg:
mkdir -p $(BUILD_DIR); cp setup.cfg $(BUILD_DIR)/setup.cfg
mkdir -p $(BUILD_DIR); cp $(SRC_DIR)/setup.cfg $(BUILD_DIR)/setup.cfg
$(BUILD_DIR)/vortex_afu.qsf:
mkdir -p $(BUILD_DIR); cp vortex_afu.qsf $(BUILD_DIR)/vortex_afu.qsf
mkdir -p $(BUILD_DIR); cp $(SRC_DIR)/vortex_afu.qsf $(BUILD_DIR)/vortex_afu.qsf
$(BUILD_DIR)/vortex_afu.json:
mkdir -p $(BUILD_DIR); cp vortex_afu.json $(BUILD_DIR)/vortex_afu.json
mkdir -p $(BUILD_DIR); cp $(SRC_DIR)/vortex_afu.json $(BUILD_DIR)/vortex_afu.json
gen-sources: $(BUILD_DIR)/sources.txt
$(BUILD_DIR)/sources.txt:

11
hw/syn/altera/quartus/Makefile
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@ -1,16 +1,19 @@
include ../common.mk
ROOT_DIR := $(realpath ../../../..)
include $(ROOT_DIR)/config.mk
PREFIX ?= build
BUILD_DIR=$(PREFIX)_$(DEVICE_FAMILY)
BUILD_DIR := $(PREFIX)_$(DEVICE_FAMILY)
IP_CACHE_DIR=../ip_cache/$(DEVICE_FAMILY)
SCRIPT_DIR := $(VORTEX_HOME)/hw/scripts
IP_CACHE_DIR := $(ROOT_DIR)/hw/syn/altera/ip_cache/$(DEVICE_FAMILY)
.PHONY: dogfood unittest pipeline lmem cache fpu core vortex top test
ip-gen: $(IP_CACHE_DIR)/ip_gen.log
$(IP_CACHE_DIR)/ip_gen.log:
../ip_gen.sh $(IP_CACHE_DIR)
$(SCRIPT_DIR)/ip_gen.sh $(IP_CACHE_DIR)
dogfood:
mkdir -p dogfood/$(BUILD_DIR)

19
hw/syn/altera/quartus/common.mk
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@ -1,11 +1,14 @@
include ../common.mk
ROOT_DIR := $(realpath ../../../../../..)
include $(ROOT_DIR)/config.mk
RTL_DIR = ../../../../../rtl
AFU_DIR = $(RTL_DIR)/afu/opae
THIRD_PARTY_DIR = ../../../../../../third_party
IP_CACHE_DIR = ../../../ip_cache/$(DEVICE_FAMILY)
SCRIPT_DIR = ../../../../../scripts
THIRD_PARTY_DIR = ../../../../../../third_party
SRC_DIR := $(VORTEX_HOME)/hw/syn/altera/quartus
RTL_DIR := $(VORTEX_HOME)/hw/rtl
AFU_DIR := $(RTL_DIR)/afu/opae
THIRD_PARTY_DIR := $(VORTEX_HOME)/third_party
SCRIPT_DIR := $(VORTEX_HOME)/hw/scripts
IP_CACHE_DIR := $(ROOT_DIR)/hw/syn/altera/ip_cache/$(DEVICE_FAMILY)
ifeq ($(DEVICE_FAMILY), stratix10)
FAMILY = "Stratix 10"
@ -77,7 +80,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES): gen-sources
quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "src"
quartus_sh -t $(SRC_DIR)/project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc $(SRC_DIR)/project.sdc -inc "src"
syn.chg:
$(STAMP) syn.chg

1
hw/syn/xilinx/common.mk
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@ -1 +0,0 @@
include ../common.mk