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Verilator bug workaround

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This was causing a buffer overflow, ignoring range checks
This commit is contained in:
Blaise Tine 2024-07-29 00:28:07 -07:00
parent 2e060faaf4
commit 03e21924f4
1 changed files with 13 additions and 11 deletions
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24
hw/rtl/libs/VX_find_first.sv
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@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -17,10 +17,10 @@
module VX_find_first #(
parameter N = 1,
parameter DATAW = 1,
parameter REVERSE = 0
parameter REVERSE = 0
) (
input wire [N-1:0][DATAW-1:0] data_in,
input wire [N-1:0] valid_in,
input wire [N-1:0] valid_in,
output wire [DATAW-1:0] data_out,
output wire valid_out
);
@ -37,10 +37,12 @@ module VX_find_first #(
assign s_n[TL+i] = REVERSE ? valid_in[N-1-i] : valid_in[i];
assign d_n[TL+i] = REVERSE ? data_in[N-1-i] : data_in[i];
end
for (genvar i = TL+N; i < TN; ++i) begin
assign s_n[i] = 0;
assign d_n[i] = '0;
if (TL < (TN-N)) begin
for (genvar i = TL+N; i < TN; ++i) begin
assign s_n[i] = 0;
assign d_n[i] = '0;
end
end
for (genvar j = 0; j < LOGN; ++j) begin
@ -48,10 +50,10 @@ module VX_find_first #(
assign s_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] | s_n[2**(j+1)-1+i*2+1];
assign d_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] ? d_n[2**(j+1)-1+i*2] : d_n[2**(j+1)-1+i*2+1];
end
end
end
assign valid_out = s_n[0];
assign data_out = d_n[0];
endmodule
`TRACING_ON