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minor update
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parent
a194521683
commit
04a96e89c9
3 changed files with 10 additions and 9 deletions
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@ -121,10 +121,13 @@ module VX_lsu_unit #(
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|| (req_is_dup & dcache_req_if.ready[0]);
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always @(posedge clk) begin
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if (reset || sent_all_ready) begin
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if (reset) begin
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req_sent_mask <= 0;
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end else begin
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req_sent_mask <= req_sent_mask | dcache_req_fire;
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if (sent_all_ready)
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req_sent_mask <= 0;
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else
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req_sent_mask <= req_sent_mask | dcache_req_fire;
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end
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end
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@ -228,8 +231,8 @@ module VX_lsu_unit #(
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case (`LSU_FMT(rsp_type))
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`FMT_B: rsp_data[i] = 32'(signed'(rsp_data_shifted[7:0]));
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`FMT_H: rsp_data[i] = 32'(signed'(rsp_data_shifted[15:0]));
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`FMT_BU: rsp_data[i] = 32'(rsp_data_shifted[7:0]);
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`FMT_HU: rsp_data[i] = 32'(rsp_data_shifted[15:0]);
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`FMT_BU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[7:0]));
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`FMT_HU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[15:0]));
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default: rsp_data[i] = rsp_data_shifted;
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endcase
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end
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3
hw/rtl/cache/VX_cache.v
vendored
3
hw/rtl/cache/VX_cache.v
vendored
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@ -168,8 +168,7 @@ module VX_cache #(
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.NUM_BANKS (NUM_BANKS)
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) flush_ctrl (
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.clk (clk),
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.reset (reset),
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.flush (flush),
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.reset (reset || flush),
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.addr_out (flush_addr),
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.valid_out (flush_enable)
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);
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5
hw/rtl/cache/VX_flush_ctrl.v
vendored
5
hw/rtl/cache/VX_flush_ctrl.v
vendored
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@ -9,8 +9,7 @@ module VX_flush_ctrl #(
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parameter NUM_BANKS = 1
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) (
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input wire clk,
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input wire reset,
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input wire flush,
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input wire reset,
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output wire [`LINE_SELECT_BITS-1:0] addr_out,
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output wire valid_out
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);
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@ -18,7 +17,7 @@ module VX_flush_ctrl #(
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reg [`LINE_SELECT_BITS-1:0] flush_ctr;
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always @(posedge clk) begin
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if (reset || flush) begin
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if (reset) begin
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flush_enable <= 1;
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flush_ctr <= 0;
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end else begin
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