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https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
minor update
This commit is contained in:
Blaise Tine
parent
ce26a0a3cc
commit
04e72a2341
1 changed files with 42 additions and 42 deletions
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -19,7 +19,7 @@ module VX_alu_muldiv #(
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_execute_if.slave execute_if,
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@ -29,7 +29,7 @@ module VX_alu_muldiv #(
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`UNUSED_PARAM (CORE_ID)
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localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES);
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localparam PID_WIDTH = `UP(PID_BITS);
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localparam TAGW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + PID_WIDTH + 1 + 1;
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localparam TAG_WIDTH = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + PID_WIDTH + 1 + 1;
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`UNUSED_VAR (execute_if.data.rs3_data)
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@ -52,34 +52,34 @@ module VX_alu_muldiv #(
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wire mul_wb_out;
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wire [PID_WIDTH-1:0] mul_pid_out;
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wire mul_sop_out, mul_eop_out;
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wire mul_valid_in = execute_if.valid && is_mulx_op;
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wire mul_ready_in;
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wire mul_valid_out;
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wire mul_ready_out;
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wire is_mulh_in = `INST_M_IS_MULH(muldiv_op);
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wire is_signed_mul_a = `INST_M_SIGNED_A(muldiv_op);
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wire is_signed_mul_b = is_signed_op;
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`ifdef IMUL_DPI
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wire [NUM_LANES-1:0][`XLEN-1:0] mul_result_tmp;
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wire [NUM_LANES-1:0][`XLEN-1:0] mul_result_tmp;
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wire mul_fire_in = mul_valid_in && mul_ready_in;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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wire [`XLEN-1:0] mul_resultl, mul_resulth;
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wire [`XLEN-1:0] mul_in1 = is_alu_w ? (execute_if.data.rs1_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs1_data[i];
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wire [`XLEN-1:0] mul_in2 = is_alu_w ? (execute_if.data.rs2_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs2_data[i];
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always @(*) begin
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wire [`XLEN-1:0] mul_in1 = is_alu_w ? (execute_if.data.rs1_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs1_data[i];
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wire [`XLEN-1:0] mul_in2 = is_alu_w ? (execute_if.data.rs2_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs2_data[i];
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always @(*) begin
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dpi_imul (mul_fire_in, is_signed_mul_a, is_signed_mul_b, mul_in1, mul_in2, mul_resultl, mul_resulth);
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end
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assign mul_result_tmp[i] = is_mulh_in ? mul_resulth : (is_alu_w ? `XLEN'($signed(mul_resultl[31:0])) : mul_resultl);
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end
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VX_shift_register #(
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.DATAW (1 + TAGW + (NUM_LANES * `XLEN)),
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.DATAW (1 + TAG_WIDTH + (NUM_LANES * `XLEN)),
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.DEPTH (`LATENCY_IMUL),
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.RESETW (1)
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) mul_shift_reg (
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@ -92,8 +92,8 @@ module VX_alu_muldiv #(
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assign mul_ready_in = mul_ready_out || ~mul_valid_out;
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`else
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`else
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wire [NUM_LANES-1:0][2*(`XLEN+1)-1:0] mul_result_tmp;
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wire is_mulh_out;
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wire is_mul_w_out;
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@ -106,7 +106,7 @@ module VX_alu_muldiv #(
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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assign mul_in1[i] = is_alu_w ? {{(`XLEN-31){execute_if.data.rs1_data[i][31]}}, execute_if.data.rs1_data[i][31:0]} : {is_signed_mul_a && execute_if.data.rs1_data[i][`XLEN-1], execute_if.data.rs1_data[i]};
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assign mul_in2[i] = is_alu_w ? {{(`XLEN-31){execute_if.data.rs2_data[i][31]}}, execute_if.data.rs2_data[i][31:0]} : {is_signed_mul_b && execute_if.data.rs2_data[i][`XLEN-1], execute_if.data.rs2_data[i]};
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end
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end
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wire mul_strode;
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wire mul_busy;
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@ -115,7 +115,7 @@ module VX_alu_muldiv #(
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.clk (clk),
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.reset (reset),
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.valid_in (mul_valid_in),
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.ready_in (mul_ready_in),
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.ready_in (mul_ready_in),
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.valid_out (mul_valid_out),
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.ready_out (mul_ready_out),
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.strobe (mul_strode),
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@ -128,31 +128,31 @@ module VX_alu_muldiv #(
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.SIGNED (1)
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) serial_mul (
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.strobe (mul_strode),
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.busy (mul_busy),
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.busy (mul_busy),
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.dataa (mul_in1),
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.datab (mul_in2),
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.result (mul_result_tmp)
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);
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reg [TAGW+2-1:0] mul_tag_r;
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reg [TAG_WIDTH+2-1:0] mul_tag_r;
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always @(posedge clk) begin
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if (mul_valid_in && mul_ready_in) begin
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mul_tag_r <= {execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, is_mulh_in, is_alu_w, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop};
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end
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end
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assign {mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, is_mulh_out, is_mul_w_out, mul_pid_out, mul_sop_out, mul_eop_out} = mul_tag_r;
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`else
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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wire [`XLEN:0] mul_in1 = {is_signed_mul_a && execute_if.data.rs1_data[i][`XLEN-1], execute_if.data.rs1_data[i]};
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wire [`XLEN:0] mul_in2 = {is_signed_mul_b && execute_if.data.rs2_data[i][`XLEN-1], execute_if.data.rs2_data[i]};
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wire [`XLEN:0] mul_in2 = {is_signed_mul_b && execute_if.data.rs2_data[i][`XLEN-1], execute_if.data.rs2_data[i]};
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VX_multiplier #(
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.A_WIDTH (`XLEN+1),
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.B_WIDTH (`XLEN+1),
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@ -165,11 +165,11 @@ module VX_alu_muldiv #(
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.dataa (mul_in1),
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.datab (mul_in2),
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.result (mul_result_tmp[i])
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);
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);
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end
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VX_shift_register #(
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.DATAW (1 + TAGW + 1 + 1),
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.DATAW (1 + TAG_WIDTH + 1 + 1),
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.DEPTH (`LATENCY_IMUL),
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.RESETW (1)
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) mul_shift_reg (
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@ -186,8 +186,8 @@ module VX_alu_muldiv #(
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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`ifdef XLEN_64
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assign mul_result_out[i] = is_mulh_out ? mul_result_tmp[i][2*(`XLEN)-1:`XLEN] :
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(is_mul_w_out ? `XLEN'($signed(mul_result_tmp[i][31:0])) :
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assign mul_result_out[i] = is_mulh_out ? mul_result_tmp[i][2*(`XLEN)-1:`XLEN] :
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(is_mul_w_out ? `XLEN'($signed(mul_result_tmp[i][31:0])) :
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mul_result_tmp[i][`XLEN-1:0]);
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`else
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assign mul_result_out[i] = is_mulh_out ? mul_result_tmp[i][2*(`XLEN)-1:`XLEN] : mul_result_tmp[i][`XLEN-1:0];
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@ -211,7 +211,7 @@ module VX_alu_muldiv #(
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wire is_rem_op = `INST_M_IS_REM(muldiv_op);
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wire div_valid_in = execute_if.valid && ~is_mulx_op;
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wire div_valid_in = execute_if.valid && ~is_mulx_op;
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wire div_ready_in;
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wire div_valid_out;
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wire div_ready_out;
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@ -226,25 +226,25 @@ module VX_alu_muldiv #(
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`else
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assign div_in1[i] = execute_if.data.rs1_data[i];
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assign div_in2[i] = execute_if.data.rs2_data[i];
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`endif
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`endif
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end
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`ifdef IDIV_DPI
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`ifdef IDIV_DPI
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wire [NUM_LANES-1:0][`XLEN-1:0] div_result_in;
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wire div_fire_in = div_valid_in && div_ready_in;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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wire [`XLEN-1:0] div_quotient, div_remainder;
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always @(*) begin
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always @(*) begin
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dpi_idiv (div_fire_in, is_signed_op, div_in1[i], div_in2[i], div_quotient, div_remainder);
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end
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assign div_result_in[i] = is_rem_op ? (is_alu_w ? `XLEN'($signed(div_remainder[31:0])) : div_remainder) :
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assign div_result_in[i] = is_rem_op ? (is_alu_w ? `XLEN'($signed(div_remainder[31:0])) : div_remainder) :
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(is_alu_w ? `XLEN'($signed(div_quotient[31:0])) : div_quotient);
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end
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VX_shift_register #(
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.DATAW (1 + TAGW + (NUM_LANES * `XLEN)),
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.DATAW (1 + TAG_WIDTH + (NUM_LANES * `XLEN)),
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.DEPTH (`LATENCY_IMUL),
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.RESETW (1)
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) div_shift_reg (
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@ -260,7 +260,7 @@ module VX_alu_muldiv #(
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`else
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wire [NUM_LANES-1:0][`XLEN-1:0] div_quotient, div_remainder;
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wire is_rem_op_out;
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wire is_rem_op_out;
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wire is_div_w_out;
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wire div_strode;
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wire div_busy;
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@ -285,31 +285,31 @@ module VX_alu_muldiv #(
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) serial_div (
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.clk (clk),
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.reset (reset),
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.strobe (div_strode),
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.busy (div_busy),
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.is_signed (is_signed_op),
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.is_signed (is_signed_op),
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.numer (div_in1),
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.denom (div_in2),
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.quotient (div_quotient),
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.remainder (div_remainder)
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.remainder (div_remainder)
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);
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reg [TAGW+2-1:0] div_tag_r;
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reg [TAG_WIDTH+2-1:0] div_tag_r;
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always @(posedge clk) begin
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if (div_valid_in && div_ready_in) begin
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div_tag_r <= {execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, is_rem_op, is_alu_w, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop};
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end
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end
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assign {div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, is_rem_op_out, is_div_w_out, div_pid_out, div_sop_out, div_eop_out} = div_tag_r;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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`ifdef XLEN_64
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assign div_result_out[i] = is_rem_op_out ? (is_div_w_out ? `XLEN'($signed(div_remainder[i][31:0])) : div_remainder[i]) :
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(is_div_w_out ? `XLEN'($signed(div_quotient[i][31:0])) : div_quotient[i]);
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assign div_result_out[i] = is_rem_op_out ? (is_div_w_out ? `XLEN'($signed(div_remainder[i][31:0])) : div_remainder[i]) :
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(is_div_w_out ? `XLEN'($signed(div_quotient[i][31:0])) : div_quotient[i]);
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`else
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assign div_result_out[i] = is_rem_op_out ? div_remainder[i] : div_quotient[i];
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`UNUSED_VAR (is_div_w_out)
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@ -323,7 +323,7 @@ module VX_alu_muldiv #(
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VX_stream_arb #(
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.NUM_INPUTS (2),
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.DATAW (TAGW + (NUM_LANES * `XLEN)),
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.DATAW (TAG_WIDTH + (NUM_LANES * `XLEN)),
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.OUT_BUF (1)
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) rsp_buf (
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.clk (clk),
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@ -337,5 +337,5 @@ module VX_alu_muldiv #(
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.ready_out (commit_if.ready),
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`UNUSED_PIN (sel_out)
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);
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endmodule
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