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https://github.com/vortexgpgpu/vortex.git
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minor update
This commit is contained in:
Blaise Tine
parent
143319d557
commit
05f93fac20
5 changed files with 32 additions and 29 deletions
38
hw/rtl/cache/VX_bank.v
vendored
38
hw/rtl/cache/VX_bank.v
vendored
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@ -154,12 +154,12 @@ module VX_bank #(
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wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen_st0, byteen_st1;
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wire [NUM_PORTS-1:0][`REQS_BITS-1:0] req_tid_st0, req_tid_st1;
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wire [NUM_PORTS-1:0] pmask_st0, pmask_st1;
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wire [`CACHE_LINE_WIDTH-1:0] data_st0, data_st1;
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wire [`CACHE_LINE_WIDTH-1:0] wdata_st0, wdata_st1;
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wire [`CACHE_LINE_WIDTH-1:0] rdata_st1;
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wire [CORE_TAG_WIDTH-1:0] tag_st0, tag_st1;
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wire valid_st0, valid_st1;
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wire is_fill_st0, is_fill_st1;
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wire is_mshr_st0, is_mshr_st1;
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wire [`CACHE_LINE_WIDTH-1:0] readdata_st1;
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wire is_mshr_st0, is_mshr_st1;
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wire miss_st0, miss_st1;
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wire prev_miss_dep_st0, prev_miss_dep_st1;
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wire force_miss_st0, force_miss_st1;
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@ -258,7 +258,7 @@ module VX_bank #(
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mshr_pop_unqual,
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drsq_pop_unqual || flush_enable,
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mshr_pop_unqual ? 1'b0 : creq_rw,
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flush_enable ? (`LINE_ADDR_WIDTH'(flush_addr)) : (mshr_pop_unqual ? mshr_addr : (dram_rsp_valid ? dram_rsp_addr_qual : creq_addr)),
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mshr_pop_unqual ? mshr_addr : (dram_rsp_valid ? dram_rsp_addr_qual : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)),
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dram_rsp_valid ? dram_rsp_data : creq_line_data,
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mshr_pop_unqual ? mshr_wsel : creq_wsel,
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mshr_pop_unqual ? mshr_byteen : creq_byteen,
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@ -267,7 +267,7 @@ module VX_bank #(
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mshr_pop_unqual ? mshr_tag : creq_tag,
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mshr_pending_sel
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}),
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.data_out ({valid_st0, is_flush_st0, is_mshr_st0, is_fill_st0, mem_rw_st0, addr_st0, data_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0, mshr_pending_st0})
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.data_out ({valid_st0, is_flush_st0, is_mshr_st0, is_fill_st0, mem_rw_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0, mshr_pending_st0})
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);
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`ifdef DBG_CACHE_REQ_INFO
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@ -330,8 +330,8 @@ module VX_bank #(
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.clk (clk),
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.reset (reset),
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.enable (1'b1),
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.data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, prev_miss_dep_st0, incoming_fill_st0, miss_st0, force_miss_st0, mem_rw_st0, addr_st0, data_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0}),
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.data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, prev_miss_dep_st1, incoming_fill_st1, miss_st1, force_miss_st1, mem_rw_st1, addr_st1, data_st1, wsel_st1, byteen_st1, req_tid_st1, pmask_st1, tag_st1})
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.data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, prev_miss_dep_st0, incoming_fill_st0, miss_st0, force_miss_st0, mem_rw_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0}),
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.data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, prev_miss_dep_st1, incoming_fill_st1, miss_st1, force_miss_st1, mem_rw_st1, addr_st1, wdata_st1, wsel_st1, byteen_st1, req_tid_st1, pmask_st1, tag_st1})
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);
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`ifdef DBG_CACHE_REQ_INFO
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@ -381,13 +381,13 @@ module VX_bank #(
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end
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VX_data_access #(
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.BANK_ID (BANK_ID),
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.CACHE_ID (CACHE_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.WRITE_ENABLE (WRITE_ENABLE)
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.BANK_ID (BANK_ID),
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.CACHE_ID (CACHE_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.CACHE_LINE_SIZE(CACHE_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.WRITE_ENABLE (WRITE_ENABLE)
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) data_access (
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.clk (clk),
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.reset (reset),
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@ -401,13 +401,13 @@ module VX_bank #(
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// reading
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.readen (valid_st1 && !mem_rw_st1 && !is_fill_st1),
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.rddata (readdata_st1),
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.rddata (rdata_st1),
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// writing
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.writeen (valid_st1 && writeen_st1),
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.is_fill (is_fill_st1),
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.byteen (line_byteen_st1),
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.wrdata (data_st1)
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.wrdata (wdata_st1)
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);
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assign mshr_push = valid_st1 && mshr_push_st1;
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@ -482,10 +482,10 @@ module VX_bank #(
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if (`WORD_SELECT_BITS != 0) begin
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for (genvar p = 0; p < NUM_PORTS; ++p) begin
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assign crsq_data[p] = readdata_st1[wsel_st1[p] * `WORD_WIDTH +: `WORD_WIDTH];
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assign crsq_data[p] = rdata_st1[wsel_st1[p] * `WORD_WIDTH +: `WORD_WIDTH];
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end
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end else begin
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assign crsq_data = readdata_st1;
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assign crsq_data = rdata_st1;
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end
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assign crsq_pmask = pmask_st1;
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@ -528,7 +528,7 @@ module VX_bank #(
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assign dreq_byteen = writeback ? line_byteen_st1 : {CACHE_LINE_SIZE{1'b1}};
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assign dreq_addr = addr_st1;
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assign dreq_data = data_st1;
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assign dreq_data = wdata_st1;
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VX_fifo_queue #(
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.DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH),
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15
hw/rtl/cache/VX_data_access.v
vendored
15
hw/rtl/cache/VX_data_access.v
vendored
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@ -27,7 +27,7 @@ module VX_data_access #(
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`endif
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`IGNORE_WARNINGS_BEGIN
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input wire[`LINE_ADDR_WIDTH-1:0] addr,
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input wire[`LINE_ADDR_WIDTH-1:0] addr,
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`IGNORE_WARNINGS_END
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// reading
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@ -41,10 +41,13 @@ module VX_data_access #(
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input wire [`CACHE_LINE_WIDTH-1:0] wrdata
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);
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`UNUSED_VAR (reset)
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`UNUSED_VAR (readen)
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wire [`LINE_SELECT_BITS-1:0] line_addr;
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wire [CACHE_LINE_SIZE-1:0] byte_enable;
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wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0];
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assign line_addr = addr[`LINE_SELECT_BITS-1:0];
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assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen;
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VX_sp_ram #(
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.DATAW(CACHE_LINE_SIZE * 8),
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@ -52,7 +55,7 @@ module VX_data_access #(
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.BYTEENW(CACHE_LINE_SIZE),
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.RWCHECK(1)
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) data_store (
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.clk(clk),
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.clk(clk),
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.addr(line_addr),
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.wren(writeen),
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.byteen(byte_enable),
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@ -60,10 +63,6 @@ module VX_data_access #(
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.din(wrdata),
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.dout(rddata)
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);
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assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen;
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`UNUSED_VAR (readen)
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`ifdef DBG_PRINT_CACHE_DATA
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always @(posedge clk) begin
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@ -2,8 +2,8 @@
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"version": 1,
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"afu-image": {
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"power": 0,
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"clock-frequency-high": "auto-200",
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"clock-frequency-low": "auto-200",
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"clock-frequency-high": "auto-210",
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"clock-frequency-low": "auto-210",
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"cmd-mem-read": 1,
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"cmd-mem-write": 2,
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@ -12,6 +12,8 @@ set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
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set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
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set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
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set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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@ -47,6 +47,8 @@ set_global_assignment -name MUX_RESTRUCTURE ON
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set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
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set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
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set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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