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adding issue_top testbench
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Blaise Tine
parent
1b9f0a998b
commit
068ec6c5ef
4 changed files with 211 additions and 1 deletions
132
hw/rtl/core/VX_issue_top.sv
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132
hw/rtl/core/VX_issue_top.sv
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_issue_top import VX_gpu_pkg::*; #(
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parameter `STRING INSTANCE_ID = "issue"
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) (
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// Clock
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input wire clk,
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input wire reset,
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input wire decode_valid,
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input wire [`UUID_WIDTH-1:0] decode_uuid,
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input wire [`NW_WIDTH-1:0] decode_wid,
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input wire [`NUM_THREADS-1:0] decode_tmask,
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input wire [`PC_BITS-1:0] decode_PC,
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input wire [`EX_BITS-1:0] decode_ex_type,
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input wire [`INST_OP_BITS-1:0] decode_op_type,
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input op_args_t decode_op_args,
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input wire decode_wb,
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input wire [`NR_BITS-1:0] decode_rd,
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input wire [`NR_BITS-1:0] decode_rs1,
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input wire [`NR_BITS-1:0] decode_rs2,
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input wire [`NR_BITS-1:0] decode_rs3,
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output wire decode_ready,
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input wire writeback_valid[`ISSUE_WIDTH],
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input wire [`UUID_WIDTH-1:0] writeback_uuid[`ISSUE_WIDTH],
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input wire [ISSUE_WIS_W-1:0] writeback_wis[`ISSUE_WIDTH],
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input wire [`NUM_THREADS-1:0] writeback_tmask[`ISSUE_WIDTH],
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input wire [`PC_BITS-1:0] writeback_PC[`ISSUE_WIDTH],
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input wire [`NR_BITS-1:0] writeback_rd[`ISSUE_WIDTH],
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input wire [`NUM_THREADS-1:0][`XLEN-1:0] writeback_data[`ISSUE_WIDTH],
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input wire writeback_sop[`ISSUE_WIDTH],
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input wire writeback_eop[`ISSUE_WIDTH],
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input wire dispatch_valid[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input wire [`UUID_WIDTH-1:0] dispatch_uuid[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input wire [ISSUE_WIS_W-1:0] dispatch_wis[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input wire [`NUM_THREADS-1:0] dispatch_tmask[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input wire [`PC_BITS-1:0] dispatch_PC[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input wire [`INST_ALU_BITS-1:0] dispatch_op_type[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input op_args_t dispatch_op_args[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input wire dispatch_wb[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input wire [`NR_BITS-1:0] dispatch_rd[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input wire [`NT_WIDTH-1:0] dispatch_tid[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input wire [`NUM_THREADS-1:0][`XLEN-1:0] dispatch_rs1_data[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input wire [`NUM_THREADS-1:0][`XLEN-1:0] dispatch_rs2_data[`NUM_EX_UNITS * `ISSUE_WIDTH],
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input wire [`NUM_THREADS-1:0][`XLEN-1:0] dispatch_rs3_data[`NUM_EX_UNITS * `ISSUE_WIDTH],
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output wire dispatch_ready[`NUM_EX_UNITS * `ISSUE_WIDTH]
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);
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VX_decode_if decode_if();
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VX_dispatch_if dispatch_if[`NUM_EX_UNITS * `ISSUE_WIDTH]();
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VX_writeback_if writeback_if[`ISSUE_WIDTH]();
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assign decode_if.valid = decode_valid;
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assign decode_if.data.uuid = decode_uuid;
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assign decode_if.data.wid = decode_wid;
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assign decode_if.data.tmask = decode_tmask;
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assign decode_if.data.PC = decode_PC;
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assign decode_if.data.ex_type = decode_ex_type;
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assign decode_if.data.op_type = decode_op_type;
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assign decode_if.data.op_args = decode_op_args;
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assign decode_if.data.wb = decode_wb;
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assign decode_if.data.rd = decode_rd;
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assign decode_if.data.rs1 = decode_rs1;
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assign decode_if.data.rs2 = decode_rs2;
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assign decode_if.data.rs3 = decode_rs3;
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assign decode_ready = decode_if.ready;
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign writeback_if[i].valid = writeback_valid[i];
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assign writeback_if[i].data.uuid = writeback_uuid[i];
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assign writeback_if[i].data.wis = writeback_wis[i];
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assign writeback_if[i].data.tmask = writeback_tmask[i];
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assign writeback_if[i].data.PC = writeback_PC[i];
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assign writeback_if[i].data.rd = writeback_rd[i];
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assign writeback_if[i].data.data = writeback_data[i];
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assign writeback_if[i].data.sop = writeback_sop[i];
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assign writeback_if[i].data.eop = writeback_eop[i];
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end
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for (genvar i = 0; i < `NUM_EX_UNITS * `ISSUE_WIDTH; ++i) begin
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assign dispatch_if[i].valid = dispatch_valid[i];
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assign dispatch_if[i].data.uuid = dispatch_uuid[i];
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assign dispatch_if[i].data.wis = dispatch_wis[i];
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assign dispatch_if[i].data.tmask = dispatch_tmask[i];
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assign dispatch_if[i].data.PC = dispatch_PC[i];
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assign dispatch_if[i].data.op_type = dispatch_op_type[i];
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assign dispatch_if[i].data.op_args = dispatch_op_args[i];
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assign dispatch_if[i].data.wb = dispatch_wb[i];
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assign dispatch_if[i].data.rd = dispatch_rd[i];
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assign dispatch_if[i].data.tid = dispatch_tid[i];
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assign dispatch_if[i].data.rs1_data = dispatch_rs1_data[i];
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assign dispatch_if[i].data.rs2_data = dispatch_rs2_data[i];
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assign dispatch_if[i].data.rs3_data = dispatch_rs3_data[i];
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assign dispatch_ready[i] = dispatch_if[i].ready;
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end
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`ifdef PERF_ENABLE
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issue_perf_t issue_perf = '0;
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`endif
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VX_issue #(
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.INSTANCE_ID (INSTANCE_ID)
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) issue (
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`SCOPE_IO_BIND (0)
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.clk (clk),
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.reset (reset),
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`ifdef PERF_ENABLE
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.issue_perf (issue_perf),
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`endif
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.decode_if (decode_if),
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.writeback_if (writeback_if),
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.dispatch_if (dispatch_if)
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);
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endmodule
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@ -4,6 +4,7 @@ all:
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$(MAKE) -C mem_streamer
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$(MAKE) -C cache_top
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$(MAKE) -C core_top
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$(MAKE) -C issue_top
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run:
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$(MAKE) -C cache run
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@ -11,10 +12,12 @@ run:
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$(MAKE) -C mem_streamer run
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$(MAKE) -C cache_top run
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$(MAKE) -C core_top run
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$(MAKE) -C issue_top run
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clean:
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$(MAKE) -C cache clean
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$(MAKE) -C generic_queue clean
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$(MAKE) -C mem_streamer clean
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$(MAKE) -C cache_top clean
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$(MAKE) -C core_top clean
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$(MAKE) -C core_top clean
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$(MAKE) -C issue_top clean
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26
hw/unittest/issue_top/Makefile
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26
hw/unittest/issue_top/Makefile
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ROOT_DIR := $(realpath ../../..)
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include $(ROOT_DIR)/config.mk
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PROJECT := issue_top
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RTL_DIR := $(VORTEX_HOME)/hw/rtl
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DPI_DIR := $(VORTEX_HOME)/hw/dpi
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SRC_DIR := $(VORTEX_HOME)/hw/unittest/$(PROJECT)
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CXXFLAGS := -I$(SRC_DIR) -I$(VORTEX_HOME)/hw/unittest/common -I$(VORTEX_HOME)/sim/common
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CXXFLAGS += -I$(ROOT_DIR)/hw
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SRCS := $(DPI_DIR)/util_dpi.cpp
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SRCS += $(SRC_DIR)/main.cpp
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DBG_TRACE_FLAGS := -DDBG_TRACE_CACHE
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RTL_PKGS := $(RTL_DIR)/VX_gpu_pkg.sv $(RTL_DIR)/core/VX_trace_pkg.sv
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RTL_INCLUDE := -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs
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RTL_INCLUDE += -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/core
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TOP := VX_issue_top
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include ../common.mk
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49
hw/unittest/issue_top/main.cpp
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49
hw/unittest/issue_top/main.cpp
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@ -0,0 +1,49 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "vl_simulator.h"
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#ifndef TRACE_START_TIME
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#define TRACE_START_TIME 0ull
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#endif
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#ifndef TRACE_STOP_TIME
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#define TRACE_STOP_TIME -1ull
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#endif
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static uint64_t timestamp = 0;
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static bool trace_enabled = false;
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static uint64_t trace_start_time = TRACE_START_TIME;
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static uint64_t trace_stop_time = TRACE_STOP_TIME;
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double sc_time_stamp() {
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return timestamp;
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}
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bool sim_trace_enabled() {
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if (timestamp >= trace_start_time
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&& timestamp < trace_stop_time)
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return true;
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return trace_enabled;
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}
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void sim_trace_enable(bool enable) {
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trace_enabled = enable;
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}
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int main(int argc, char **argv) {
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// Initialize Verilators variables
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Verilated::commandArgs(argc, argv);
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return 0;
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}
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