minor update

docs/altera_fpga_guide.md

@@ -76,8 +76,8 @@ Run the following from your Vortex build directory
 
     $ TARGET=fpga ./ci/blackbox.sh --driver=opae --app=sgemm --args="-n128"
 
-Testing OPAE Synthesis using Intel ASE Simulation
--------------------------------------------------
+Testing Vortex using OPAE with Intel ASE Simulation
+---------------------------------------------------
 
 Building ASE synthesis
 

docs/xilinx_fpga_guide.md

@@ -33,4 +33,20 @@ Ensure you have the correct opae runtime for the FPGA target
 
 Run the following from your Vortex build directory
 
-    $ TARGET=hw FPGA_BIN_DIR=<BUILD_DIR>/bin ./ci/blackbox.sh --driver=xrt --app=sgemm --args="-n128"
+    $ TARGET=hw FPGA_BIN_DIR=<BUILD_DIR>/bin ./ci/blackbox.sh --driver=xrt --app=sgemm --args="-n128"
+
+Testing Vortex using XRT Hardware Emulation
+-------------------------------------------
+
+Building XRT's hw_emu target
+
+    $ cd hw/syn/xilinx/xrt
+    $ PREFIX=test2 PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 TARGET=hw_emu make
+
+Building XRT hw_meu runtime
+
+    $ TARGET=hw_emu make -C runtime/xrt
+
+Running XRT hw_emu simulation
+
+    $ TARGET=hw_emu FPGA_BIN_DIR=<BUILD_DIR>/bin ./ci/blackbox.sh --driver=xrt --app=sgemm

hw/rtl/libs/VX_mem_scheduler.sv

@@ -223,8 +223,6 @@ module VX_mem_scheduler #(
 
     if (COALESCE_ENABLE) begin
 
-        `RESET_RELAY (coalescer_reset, reset);
-
         VX_mem_coalescer #(
             .INSTANCE_ID    ($sformatf("%s-coalescer", INSTANCE_ID)),
             .NUM_REQS       (CORE_REQS),
@@ -236,8 +234,8 @@ module VX_mem_scheduler #(
             .UUID_WIDTH     (UUID_WIDTH),
             .QUEUE_SIZE     (MEM_QUEUE_SIZE)
         ) coalescer (
-            .clk   (clk),
-            .reset (coalescer_reset),
+            .clk            (clk),
+            .reset          (reset),
 
             // Input request
             .in_req_valid   (reqq_valid),