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minor update

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This commit is contained in:
Blaise Tine 2022-05-19 02:33:53 -04:00
parent c9601978cf
commit 0715867fa6
4 changed files with 11 additions and 11 deletions
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4
hw/rtl/cache/VX_rsp_merge.sv vendored
View file

@ -67,8 +67,8 @@ module VX_rsp_merge #(
for (integer i = 0; i < NUM_REQS; ++i) begin
for (integer j = 0; j < NUM_BANKS * NUM_PORTS; ++j) begin
integer p = j[0 +: PORTS_BITS];
integer b = j[PORTS_BITS +: BANK_SEL_BITS];
automatic integer p = j[0 +: PORTS_BITS];
automatic integer b = j[PORTS_BITS +: BANK_SEL_BITS];
if (per_bank_core_rsp_valid[b]
&& per_bank_core_rsp_pmask[b][p]
&& per_bank_core_rsp_idx[b][p] == `UP(REQ_SEL_BITS)'(i)) begin

6
hw/rtl/raster_unit/VX_raster_be.sv
View file

@ -115,10 +115,10 @@ module VX_raster_be #(
always @(*) begin
for (integer i = 0; i < OUTPUT_BATCHES; ++i) begin
fifo_mask_in = 0;
fifo_stamp_in = 'x;
fifo_mask_in[i] = 0;
fifo_stamp_in[i] = 'x;
for (integer j = 0; j < OUTPUT_QUADS; ++j) begin
integer ii = i * OUTPUT_QUADS + j;
automatic integer ii = i * OUTPUT_QUADS + j;
if (ii < PER_BLOCK_QUADS) begin
fifo_mask_in[i][j] = qe_valid[ii];
fifo_stamp_in[i][j].pos_x = qe_x_loc[ii][`RASTER_DIM_BITS-1:1];

10
hw/rtl/raster_unit/VX_raster_mem.sv
View file

@ -155,13 +155,13 @@ module VX_raster_mem #(
mem_req_mask <= TILE_FETCH_MASK;
mem_req_tag <= 'x;
curr_tbuf_addr <= curr_tbuf_addr + 4 + 4;
curr_num_tiles <= curr_num_tiles - 1;
curr_num_tiles <= curr_num_tiles - `RASTER_TILE_BITS'(1);
end else begin
// done, return to idle
state <= STATE_IDLE;
end
end
rem_num_prims <= rem_num_prims - 1;
rem_num_prims <= rem_num_prims - `RASTER_PID_BITS'(1);
end else
if (fsm_req_fire) begin
// send next primitive address
@ -171,7 +171,7 @@ module VX_raster_mem #(
mem_req_mask <= PID_FETCH_MASK;
mem_req_tag <= 'x;
curr_tbuf_addr <= curr_tbuf_addr + 4;
curr_num_prims <= curr_num_prims - 1;
curr_num_prims <= curr_num_prims - `RASTER_PID_BITS'(1);
end
end
end
@ -273,8 +273,8 @@ module VX_raster_mem #(
// Output buffer
wire buf_out_valid = prim_data_rsp_valid
&& ~prim_addr_rsp_valid;
assign buf_out_valid = prim_data_rsp_valid
&& ~prim_addr_rsp_valid;
`UNUSED_VAR (mem_rsp_mask)

2
hw/rtl/raster_unit/VX_raster_te.sv
View file

@ -118,7 +118,7 @@ module VX_raster_te #(
wire tile_valid_e = tile_valid && ((eval0 >= 0) && (eval1 >= 0) && (eval2 >= 0));
// Generate sub-tile info
wire [`RASTER_DIM_BITS-1:0] subtile_logsize = `RASTER_DIM_BITS'(TILE_LOGSIZE) - `RASTER_DIM_BITS'(tile_level) - 1;
wire [`RASTER_DIM_BITS-1:0] subtile_logsize = `RASTER_DIM_BITS'(TILE_LOGSIZE-1) - `RASTER_DIM_BITS'(tile_level);
wire is_block = (subtile_logsize < `RASTER_DIM_BITS'(BLOCK_LOGSIZE));
assign subtile_level = tile_level + LEVEL_BITS'(1);
for (genvar i = 0; i < 2; ++i) begin