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minor update

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This commit is contained in:
Blaise Tine 2021-02-12 08:52:06 -08:00
parent ab63ac9e5d
commit 073964fdf7
8 changed files with 59 additions and 59 deletions
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2
hw/rtl/VX_config.vh
View file

@ -313,7 +313,7 @@
// Miss Handling Register Size
`ifndef DMSHR_SIZE
`define DMSHR_SIZE `LSUQ_SIZE
`define DMSHR_SIZE (`LSUQ_SIZE / 2)
`endif
// DRAM Request Queue Size

3
hw/rtl/VX_csr_arb.v
View file

@ -66,7 +66,8 @@ module VX_csr_arb #(
VX_stream_arbiter #(
.NUM_REQS (NUM_REQS),
.DATAW (RSP_DATAW),
.BUFFERED (BUFFERED_RSP)
.BUFFERED (BUFFERED_RSP),
.TYPE ("X") // fixed arbitration
) rsp_arb (
.clk (clk),
.reset (reset),

16
hw/rtl/fp_cores/VX_fp_div.v
View file

@ -29,7 +29,17 @@ module VX_fp_div #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
for (genvar i = 0; i < LANES; i++) begin
for (genvar i = 0; i < LANES; i++) begin
wire fdiv_reset;
VX_reset_relay #(
.NUM_NODES(1)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fdiv_reset)
);
`ifdef VERILATOR
reg [31:0] r;
fflags_t f;
@ -45,7 +55,7 @@ module VX_fp_div #(
.RESETW (1)
) shift_req_dpi (
.clk (clk),
.reset (reset),
.reset (fdiv_reset),
.enable (enable),
.data_in (r),
.data_out (result[i])
@ -53,7 +63,7 @@ module VX_fp_div #(
`else
acl_fdiv fdiv (
.clk (clk),
.areset (reset),
.areset (fdiv_reset),
.en (enable),
.a (dataa[i]),
.b (datab[i]),

16
hw/rtl/fp_cores/VX_fp_sqrt.v
View file

@ -28,7 +28,17 @@ module VX_fp_sqrt #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
for (genvar i = 0; i < LANES; i++) begin
for (genvar i = 0; i < LANES; i++) begin
wire fsqrt_reset;
VX_reset_relay #(
.NUM_NODES(1)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fsqrt_reset)
);
`ifdef VERILATOR
reg [31:0] r;
fflags_t f;
@ -44,7 +54,7 @@ module VX_fp_sqrt #(
.RESETW (1)
) shift_req_dpi (
.clk (clk),
.reset (reset),
.reset (fsqrt_reset),
.enable (enable),
.data_in (r),
.data_out (result[i])
@ -52,7 +62,7 @@ module VX_fp_sqrt #(
`else
acl_fsqrt fsqrt (
.clk (clk),
.areset (reset),
.areset (fsqrt_reset),
.en (enable),
.a (dataa[i]),
.q (result[i])

2
hw/rtl/libs/VX_stream_arbiter.v
View file

@ -16,7 +16,7 @@ module VX_stream_arbiter #(
output wire valid_out,
output wire [DATAW-1:0] data_out,
input wire ready_out
);
);
localparam LOG_NUM_REQS = $clog2(NUM_REQS);

21
hw/syn/opae/README
View file

@ -23,10 +23,10 @@ cd build_fpga && qsub-synth
tail -n 10 ./build_fpga_1c/build.log
# Check if the job is submitted to the queue and running. Status should be R
qstat | grep tinebp
qstat | grep <user>
# Constantly monitoring the job submitted to the queue. Stop this using Ctrl+C
watch ‘qstat | grep tinebp’
watch ‘qstat | grep <user>’
#
## Executing on FPGA
@ -90,14 +90,6 @@ tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log
tar -zxvf vortex.vcd.tar.gz
tar -xvf vortex.vcd.tar.bz2
# launch Gtkwave
gtkwave ./build_ase_1c/work/vortex.vcd &
# kill process by Users
ps -u tinebp
kill -9 <pid>
ps -u tinebp | grep "blackbox" | awk '{print $1}' | xargs kill -9
# fixing device resource busy issue when deleting /build_ase_1c/
lsof +D build_ase_1c
@ -113,11 +105,4 @@ make -C top1 clean && make -C top1 > top1/build.log 2>&1 &
make -C top2 clean && make -C top2 > top2/build.log 2>&1 &
make -C top8 clean && make -C top8 > top8/build.log 2>&1 &
make -C top16 clean && make -C top16 > top16/build.log 2>&1 &
make -C top32 clean && make -C top32 > top32/build.log 2>&1 &
# How to calculate the maximum operating frequency?
200 Mhz -> period = 1/200x10^6 = 5ns
if slack = +1.664 -> minimal period = 5-1.664 = 3.336 -> fmax = 1/3.336 = 300 Mhz
# build rtlsim from driver tests
make -C ../../rtlsim clean && reset && make -C ../../rtlsim
make -C top32 clean && make -C top32 > top32/build.log 2>&1 &

29
hw/syn/opae/vortex_afu.qsf
View file

@ -10,19 +10,16 @@ set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
#set_global_assignment -name OPTIMIZATION_TECHNIQUE BALANCED
#set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
#set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
#set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
#set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
#set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
#set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
#set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
#set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
#set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
#set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
#set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
#set_global_assignment -name POWER_USE_TA_VALUE 65
#set_global_assignment -name SEED 1
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name SEED 1

29
hw/syn/quartus/project.tcl
View file

@ -45,22 +45,19 @@ set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name USE_HIGH_SPEED_ADDER ON
set_global_assignment -name MUX_RESTRUCTURE ON
#set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
#set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
#set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
#set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
#set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
#set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
#set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
#set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
#set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
#set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
#set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
#set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
#set_global_assignment -name POWER_USE_TA_VALUE 65
#set_global_assignment -name SEED 1
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name SEED 1
switch $opts(family) {
"Arria 10" {