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Adds the riscv vector extension into simx
Added vector regression test to ci.yml
This commit is contained in:
MichaelJSr
parent
8230b37411
commit
073e0ddd10
23 changed files with 5718 additions and 106 deletions
486
sim/common/softfloat_ext.cpp
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486
sim/common/softfloat_ext.cpp
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@ -0,0 +1,486 @@
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/*============================================================================
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This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
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Package, Release 3e, by John R. Hauser.
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Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
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California. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions, and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions, and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the University nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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=============================================================================*/
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#include <assert.h>
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#include <stdbool.h>
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#include <internals.h>
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#include <../RISCV/specialize.h>
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#include <softfloat.h>
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#include "softfloat_ext.h"
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uint_fast16_t f16_classify( float16_t a )
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{
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union ui16_f16 uA;
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uint_fast16_t uiA;
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uA.f = a;
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uiA = uA.ui;
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uint_fast16_t infOrNaN = expF16UI( uiA ) == 0x1F;
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uint_fast16_t subnormalOrZero = expF16UI( uiA ) == 0;
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bool sign = signF16UI( uiA );
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bool fracZero = fracF16UI( uiA ) == 0;
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bool isNaN = isNaNF16UI( uiA );
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bool isSNaN = softfloat_isSigNaNF16UI( uiA );
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return
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( sign && infOrNaN && fracZero ) << 0 |
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( sign && !infOrNaN && !subnormalOrZero ) << 1 |
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( sign && subnormalOrZero && !fracZero ) << 2 |
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( sign && subnormalOrZero && fracZero ) << 3 |
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( !sign && infOrNaN && fracZero ) << 7 |
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( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
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( !sign && subnormalOrZero && !fracZero ) << 5 |
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( !sign && subnormalOrZero && fracZero ) << 4 |
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( isNaN && isSNaN ) << 8 |
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( isNaN && !isSNaN ) << 9;
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}
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uint_fast16_t f32_classify( float32_t a )
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{
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union ui32_f32 uA;
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uint_fast32_t uiA;
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uA.f = a;
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uiA = uA.ui;
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uint_fast16_t infOrNaN = expF32UI( uiA ) == 0xFF;
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uint_fast16_t subnormalOrZero = expF32UI( uiA ) == 0;
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bool sign = signF32UI( uiA );
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bool fracZero = fracF32UI( uiA ) == 0;
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bool isNaN = isNaNF32UI( uiA );
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bool isSNaN = softfloat_isSigNaNF32UI( uiA );
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return
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( sign && infOrNaN && fracZero ) << 0 |
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( sign && !infOrNaN && !subnormalOrZero ) << 1 |
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( sign && subnormalOrZero && !fracZero ) << 2 |
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( sign && subnormalOrZero && fracZero ) << 3 |
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( !sign && infOrNaN && fracZero ) << 7 |
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( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
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( !sign && subnormalOrZero && !fracZero ) << 5 |
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( !sign && subnormalOrZero && fracZero ) << 4 |
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( isNaN && isSNaN ) << 8 |
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( isNaN && !isSNaN ) << 9;
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}
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uint_fast16_t f64_classify( float64_t a )
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{
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union ui64_f64 uA;
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uint_fast64_t uiA;
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uA.f = a;
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uiA = uA.ui;
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uint_fast16_t infOrNaN = expF64UI( uiA ) == 0x7FF;
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uint_fast16_t subnormalOrZero = expF64UI( uiA ) == 0;
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bool sign = signF64UI( uiA );
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bool fracZero = fracF64UI( uiA ) == 0;
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bool isNaN = isNaNF64UI( uiA );
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bool isSNaN = softfloat_isSigNaNF64UI( uiA );
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return
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( sign && infOrNaN && fracZero ) << 0 |
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( sign && !infOrNaN && !subnormalOrZero ) << 1 |
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( sign && subnormalOrZero && !fracZero ) << 2 |
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( sign && subnormalOrZero && fracZero ) << 3 |
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( !sign && infOrNaN && fracZero ) << 7 |
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( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
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( !sign && subnormalOrZero && !fracZero ) << 5 |
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( !sign && subnormalOrZero && fracZero ) << 4 |
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( isNaN && isSNaN ) << 8 |
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( isNaN && !isSNaN ) << 9;
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}
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static inline uint64_t extract64(uint64_t val, int pos, int len)
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{
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assert(pos >= 0 && len > 0 && len <= 64 - pos);
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return (val >> pos) & (~UINT64_C(0) >> (64 - len));
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}
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static inline uint64_t make_mask64(int pos, int len)
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{
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assert(pos >= 0 && len > 0 && pos < 64 && len <= 64);
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return (UINT64_MAX >> (64 - len)) << pos;
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}
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//user needs to truncate output to required length
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static inline uint64_t rsqrte7(uint64_t val, int e, int s, bool sub) {
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uint64_t exp = extract64(val, s, e);
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uint64_t sig = extract64(val, 0, s);
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uint64_t sign = extract64(val, s + e, 1);
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const int p = 7;
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static const uint8_t table[] = {
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52, 51, 50, 48, 47, 46, 44, 43,
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42, 41, 40, 39, 38, 36, 35, 34,
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33, 32, 31, 30, 30, 29, 28, 27,
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26, 25, 24, 23, 23, 22, 21, 20,
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19, 19, 18, 17, 16, 16, 15, 14,
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14, 13, 12, 12, 11, 10, 10, 9,
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9, 8, 7, 7, 6, 6, 5, 4,
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4, 3, 3, 2, 2, 1, 1, 0,
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127, 125, 123, 121, 119, 118, 116, 114,
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113, 111, 109, 108, 106, 105, 103, 102,
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100, 99, 97, 96, 95, 93, 92, 91,
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90, 88, 87, 86, 85, 84, 83, 82,
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80, 79, 78, 77, 76, 75, 74, 73,
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72, 71, 70, 70, 69, 68, 67, 66,
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65, 64, 63, 63, 62, 61, 60, 59,
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59, 58, 57, 56, 56, 55, 54, 53};
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if (sub) {
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while (extract64(sig, s - 1, 1) == 0)
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exp--, sig <<= 1;
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sig = (sig << 1) & make_mask64(0 ,s);
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}
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int idx = ((exp & 1) << (p-1)) | (sig >> (s-p+1));
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uint64_t out_sig = (uint64_t)(table[idx]) << (s-p);
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uint64_t out_exp = (3 * make_mask64(0, e - 1) + ~exp) / 2;
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return (sign << (s+e)) | (out_exp << s) | out_sig;
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}
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float16_t f16_rsqrte7(float16_t in)
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{
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union ui16_f16 uA;
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uA.f = in;
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unsigned int ret = f16_classify(in);
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bool sub = false;
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switch(ret) {
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case 0x001: // -inf
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case 0x002: // -normal
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case 0x004: // -subnormal
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case 0x100: // sNaN
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softfloat_exceptionFlags |= softfloat_flag_invalid;
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[[fallthrough]];
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case 0x200: //qNaN
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uA.ui = defaultNaNF16UI;
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break;
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case 0x008: // -0
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uA.ui = 0xfc00;
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softfloat_exceptionFlags |= softfloat_flag_infinite;
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break;
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case 0x010: // +0
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uA.ui = 0x7c00;
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softfloat_exceptionFlags |= softfloat_flag_infinite;
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break;
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case 0x080: //+inf
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uA.ui = 0x0;
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break;
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case 0x020: //+ sub
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sub = true;
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[[fallthrough]];
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default: // +num
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uA.ui = rsqrte7(uA.ui, 5, 10, sub);
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break;
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}
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return uA.f;
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}
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float32_t f32_rsqrte7(float32_t in)
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{
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union ui32_f32 uA;
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uA.f = in;
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unsigned int ret = f32_classify(in);
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bool sub = false;
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switch(ret) {
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case 0x001: // -inf
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case 0x002: // -normal
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case 0x004: // -subnormal
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case 0x100: // sNaN
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softfloat_exceptionFlags |= softfloat_flag_invalid;
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[[fallthrough]];
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case 0x200: //qNaN
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uA.ui = defaultNaNF32UI;
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break;
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case 0x008: // -0
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uA.ui = 0xff800000;
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softfloat_exceptionFlags |= softfloat_flag_infinite;
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break;
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case 0x010: // +0
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uA.ui = 0x7f800000;
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softfloat_exceptionFlags |= softfloat_flag_infinite;
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break;
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case 0x080: //+inf
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uA.ui = 0x0;
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break;
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case 0x020: //+ sub
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sub = true;
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[[fallthrough]];
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default: // +num
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uA.ui = rsqrte7(uA.ui, 8, 23, sub);
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break;
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}
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return uA.f;
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}
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float64_t f64_rsqrte7(float64_t in)
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{
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union ui64_f64 uA;
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uA.f = in;
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unsigned int ret = f64_classify(in);
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bool sub = false;
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switch(ret) {
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case 0x001: // -inf
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case 0x002: // -normal
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case 0x004: // -subnormal
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case 0x100: // sNaN
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softfloat_exceptionFlags |= softfloat_flag_invalid;
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[[fallthrough]];
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case 0x200: //qNaN
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uA.ui = defaultNaNF64UI;
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break;
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case 0x008: // -0
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uA.ui = 0xfff0000000000000ul;
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softfloat_exceptionFlags |= softfloat_flag_infinite;
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break;
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case 0x010: // +0
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uA.ui = 0x7ff0000000000000ul;
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softfloat_exceptionFlags |= softfloat_flag_infinite;
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break;
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case 0x080: //+inf
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uA.ui = 0x0;
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break;
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case 0x020: //+ sub
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sub = true;
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[[fallthrough]];
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default: // +num
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uA.ui = rsqrte7(uA.ui, 11, 52, sub);
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break;
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}
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return uA.f;
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}
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//user needs to truncate output to required length
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static inline uint64_t recip7(uint64_t val, int e, int s, int rm, bool sub,
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bool *round_abnormal)
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{
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uint64_t exp = extract64(val, s, e);
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uint64_t sig = extract64(val, 0, s);
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uint64_t sign = extract64(val, s + e, 1);
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const int p = 7;
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static const uint8_t table[] = {
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127, 125, 123, 121, 119, 117, 116, 114,
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112, 110, 109, 107, 105, 104, 102, 100,
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99, 97, 96, 94, 93, 91, 90, 88,
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87, 85, 84, 83, 81, 80, 79, 77,
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76, 75, 74, 72, 71, 70, 69, 68,
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66, 65, 64, 63, 62, 61, 60, 59,
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58, 57, 56, 55, 54, 53, 52, 51,
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50, 49, 48, 47, 46, 45, 44, 43,
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42, 41, 40, 40, 39, 38, 37, 36,
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35, 35, 34, 33, 32, 31, 31, 30,
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29, 28, 28, 27, 26, 25, 25, 24,
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23, 23, 22, 21, 21, 20, 19, 19,
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18, 17, 17, 16, 15, 15, 14, 14,
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13, 12, 12, 11, 11, 10, 9, 9,
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8, 8, 7, 7, 6, 5, 5, 4,
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4, 3, 3, 2, 2, 1, 1, 0};
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if (sub) {
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while (extract64(sig, s - 1, 1) == 0)
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exp--, sig <<= 1;
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sig = (sig << 1) & make_mask64(0 ,s);
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if (exp != 0 && exp != UINT64_MAX) {
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*round_abnormal = true;
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if (rm == 1 ||
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(rm == 2 && !sign) ||
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(rm == 3 && sign))
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return ((sign << (s+e)) | make_mask64(s, e)) - 1;
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else
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return (sign << (s+e)) | make_mask64(s, e);
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}
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}
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int idx = sig >> (s-p);
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uint64_t out_sig = (uint64_t)(table[idx]) << (s-p);
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uint64_t out_exp = 2 * make_mask64(0, e - 1) + ~exp;
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if (out_exp == 0 || out_exp == UINT64_MAX) {
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out_sig = (out_sig >> 1) | make_mask64(s - 1, 1);
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if (out_exp == UINT64_MAX) {
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out_sig >>= 1;
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out_exp = 0;
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}
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}
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return (sign << (s+e)) | (out_exp << s) | out_sig;
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}
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float16_t f16_recip7(float16_t in)
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{
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union ui16_f16 uA;
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uA.f = in;
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unsigned int ret = f16_classify(in);
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bool sub = false;
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bool round_abnormal = false;
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switch(ret) {
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case 0x001: // -inf
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uA.ui = 0x8000;
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break;
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case 0x080: //+inf
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uA.ui = 0x0;
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break;
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case 0x008: // -0
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uA.ui = 0xfc00;
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softfloat_exceptionFlags |= softfloat_flag_infinite;
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break;
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case 0x010: // +0
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uA.ui = 0x7c00;
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softfloat_exceptionFlags |= softfloat_flag_infinite;
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break;
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case 0x100: // sNaN
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softfloat_exceptionFlags |= softfloat_flag_invalid;
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[[fallthrough]];
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case 0x200: //qNaN
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uA.ui = defaultNaNF16UI;
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break;
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case 0x004: // -subnormal
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case 0x020: //+ sub
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sub = true;
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[[fallthrough]];
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default: // +- normal
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uA.ui = recip7(uA.ui, 5, 10,
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softfloat_roundingMode, sub, &round_abnormal);
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if (round_abnormal)
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softfloat_exceptionFlags |= softfloat_flag_inexact |
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softfloat_flag_overflow;
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break;
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}
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return uA.f;
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}
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float32_t f32_recip7(float32_t in)
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{
|
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union ui32_f32 uA;
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|
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uA.f = in;
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unsigned int ret = f32_classify(in);
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bool sub = false;
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bool round_abnormal = false;
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switch(ret) {
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case 0x001: // -inf
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uA.ui = 0x80000000;
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break;
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case 0x080: //+inf
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uA.ui = 0x0;
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break;
|
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case 0x008: // -0
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uA.ui = 0xff800000;
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softfloat_exceptionFlags |= softfloat_flag_infinite;
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break;
|
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case 0x010: // +0
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uA.ui = 0x7f800000;
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softfloat_exceptionFlags |= softfloat_flag_infinite;
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break;
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case 0x100: // sNaN
|
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softfloat_exceptionFlags |= softfloat_flag_invalid;
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[[fallthrough]];
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case 0x200: //qNaN
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uA.ui = defaultNaNF32UI;
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break;
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case 0x004: // -subnormal
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case 0x020: //+ sub
|
||||
sub = true;
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||||
[[fallthrough]];
|
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default: // +- normal
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uA.ui = recip7(uA.ui, 8, 23,
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softfloat_roundingMode, sub, &round_abnormal);
|
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if (round_abnormal)
|
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softfloat_exceptionFlags |= softfloat_flag_inexact |
|
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softfloat_flag_overflow;
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||||
break;
|
||||
}
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||||
|
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return uA.f;
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}
|
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|
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float64_t f64_recip7(float64_t in)
|
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{
|
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union ui64_f64 uA;
|
||||
|
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uA.f = in;
|
||||
unsigned int ret = f64_classify(in);
|
||||
bool sub = false;
|
||||
bool round_abnormal = false;
|
||||
switch(ret) {
|
||||
case 0x001: // -inf
|
||||
uA.ui = 0x8000000000000000;
|
||||
break;
|
||||
case 0x080: //+inf
|
||||
uA.ui = 0x0;
|
||||
break;
|
||||
case 0x008: // -0
|
||||
uA.ui = 0xfff0000000000000;
|
||||
softfloat_exceptionFlags |= softfloat_flag_infinite;
|
||||
break;
|
||||
case 0x010: // +0
|
||||
uA.ui = 0x7ff0000000000000;
|
||||
softfloat_exceptionFlags |= softfloat_flag_infinite;
|
||||
break;
|
||||
case 0x100: // sNaN
|
||||
softfloat_exceptionFlags |= softfloat_flag_invalid;
|
||||
[[fallthrough]];
|
||||
case 0x200: //qNaN
|
||||
uA.ui = defaultNaNF64UI;
|
||||
break;
|
||||
case 0x004: // -subnormal
|
||||
case 0x020: //+ sub
|
||||
sub = true;
|
||||
[[fallthrough]];
|
||||
default: // +- normal
|
||||
uA.ui = recip7(uA.ui, 11, 52,
|
||||
softfloat_roundingMode, sub, &round_abnormal);
|
||||
if (round_abnormal)
|
||||
softfloat_exceptionFlags |= softfloat_flag_inexact |
|
||||
softfloat_flag_overflow;
|
||||
break;
|
||||
}
|
||||
|
||||
return uA.f;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue