mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
minor update
This commit is contained in:
Blaise Tine
parent
2eeb2ac532
commit
07ce16e75c
3 changed files with 31 additions and 47 deletions
32
hw/rtl/cache/VX_cache_bank.sv
vendored
32
hw/rtl/cache/VX_cache_bank.sv
vendored
|
|
@ -351,14 +351,12 @@ module VX_cache_bank #(
|
|||
|
||||
.req_uuid (req_uuid_st0),
|
||||
|
||||
.stall (pipe_stall),
|
||||
|
||||
// init/flush/fill/write/lookup
|
||||
.init (do_init_st0),
|
||||
.flush (do_flush_st0),
|
||||
.fill (do_fill_st0),
|
||||
.write (do_cache_wr_st0),
|
||||
.lookup (do_lookup_st0),
|
||||
.flush (do_flush_st0 && ~pipe_stall),
|
||||
.fill (do_fill_st0 && ~pipe_stall),
|
||||
.write (do_cache_wr_st0 && ~pipe_stall),
|
||||
.lookup (do_lookup_st0 && ~pipe_stall),
|
||||
.line_addr (addr_st0),
|
||||
.way_idx (flush_way_st0),
|
||||
|
||||
|
|
@ -458,16 +456,12 @@ module VX_cache_bank #(
|
|||
) cache_data (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
|
||||
.req_uuid (req_uuid_st1),
|
||||
|
||||
.stall (pipe_stall),
|
||||
|
||||
.init (do_init_st1),
|
||||
.read (do_cache_rd_st1),
|
||||
.fill (do_fill_st1),
|
||||
.flush (do_flush_st1),
|
||||
.write (do_cache_wr_st1),
|
||||
.fill (do_fill_st1 && ~pipe_stall),
|
||||
.flush (do_flush_st1 && ~pipe_stall),
|
||||
.write (do_cache_wr_st1 && ~pipe_stall),
|
||||
.read (do_cache_rd_st1 && ~pipe_stall),
|
||||
.way_idx (way_idx_st1),
|
||||
.line_addr (addr_st1),
|
||||
.word_idx (word_idx_st1),
|
||||
|
|
@ -481,10 +475,10 @@ module VX_cache_bank #(
|
|||
|
||||
wire [MSHR_SIZE-1:0] mshr_lookup_pending_st0;
|
||||
wire [MSHR_SIZE-1:0] mshr_lookup_rw_st0;
|
||||
wire mshr_allocate_st0 = valid_st0 && is_creq_st0 && ~pipe_stall;
|
||||
wire mshr_allocate_st0 = valid_st0 && is_creq_st0;
|
||||
wire mshr_lookup_st0 = mshr_allocate_st0;
|
||||
|
||||
wire mshr_finalize_st1 = valid_st1 && is_creq_st1 && ~pipe_stall;
|
||||
wire mshr_finalize_st1 = valid_st1 && is_creq_st1;
|
||||
|
||||
// release allocated mshr entry if we had a hit
|
||||
wire mshr_release_st1;
|
||||
|
|
@ -541,7 +535,7 @@ module VX_cache_bank #(
|
|||
.dequeue_ready (replay_ready),
|
||||
|
||||
// allocate
|
||||
.allocate_valid (mshr_allocate_st0),
|
||||
.allocate_valid (mshr_allocate_st0 && ~pipe_stall),
|
||||
.allocate_addr (addr_st0),
|
||||
.allocate_rw (rw_st0),
|
||||
.allocate_data ({word_idx_st0, byteen_st0, write_data_st0, tag_st0, req_idx_st0}),
|
||||
|
|
@ -550,13 +544,13 @@ module VX_cache_bank #(
|
|||
`UNUSED_PIN (allocate_ready),
|
||||
|
||||
// lookup
|
||||
.lookup_valid (mshr_lookup_st0),
|
||||
.lookup_valid (mshr_lookup_st0 && ~pipe_stall),
|
||||
.lookup_addr (addr_st0),
|
||||
.lookup_pending (mshr_lookup_pending_st0),
|
||||
.lookup_rw (mshr_lookup_rw_st0),
|
||||
|
||||
// finalize
|
||||
.finalize_valid (mshr_finalize_st1),
|
||||
.finalize_valid (mshr_finalize_st1 && ~pipe_stall),
|
||||
.finalize_release(mshr_release_st1),
|
||||
.finalize_pending(mshr_pending_st1),
|
||||
.finalize_id (mshr_id_st1),
|
||||
|
|
|
|||
21
hw/rtl/cache/VX_cache_data.sv
vendored
21
hw/rtl/cache/VX_cache_data.sv
vendored
|
|
@ -42,13 +42,11 @@ module VX_cache_data #(
|
|||
input wire[`UP(UUID_WIDTH)-1:0] req_uuid,
|
||||
`IGNORE_UNUSED_END
|
||||
|
||||
input wire stall,
|
||||
|
||||
input wire init,
|
||||
input wire read,
|
||||
input wire fill,
|
||||
input wire flush,
|
||||
input wire write,
|
||||
input wire read,
|
||||
input wire [`CS_LINE_ADDR_WIDTH-1:0] line_addr,
|
||||
input wire [`UP(`CS_WORD_SEL_BITS)-1:0] word_idx,
|
||||
input wire [`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] fill_data,
|
||||
|
|
@ -62,7 +60,6 @@ module VX_cache_data #(
|
|||
`UNUSED_SPARAM (INSTANCE_ID)
|
||||
`UNUSED_PARAM (BANK_ID)
|
||||
`UNUSED_PARAM (WORD_SIZE)
|
||||
`UNUSED_VAR (stall)
|
||||
`UNUSED_VAR (line_addr)
|
||||
`UNUSED_VAR (init)
|
||||
`UNUSED_VAR (read)
|
||||
|
|
@ -111,8 +108,8 @@ module VX_cache_data #(
|
|||
) byteen_store (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.read (bs_read && ~stall),
|
||||
.write (bs_write && ~stall),
|
||||
.read (bs_read),
|
||||
.write (bs_write),
|
||||
.wren (1'b1),
|
||||
.addr (line_idx),
|
||||
.wdata (bs_wdata),
|
||||
|
|
@ -166,8 +163,8 @@ module VX_cache_data #(
|
|||
) data_store (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.read (line_read && ~stall),
|
||||
.write (line_write && ~stall),
|
||||
.read (line_read),
|
||||
.write (line_write),
|
||||
.wren (line_wren),
|
||||
.addr (line_idx),
|
||||
.wdata (line_wdata),
|
||||
|
|
@ -195,16 +192,16 @@ module VX_cache_data #(
|
|||
|
||||
`ifdef DBG_TRACE_CACHE
|
||||
always @(posedge clk) begin
|
||||
if (fill && ~stall) begin
|
||||
if (fill) begin
|
||||
`TRACE(3, ("%t: %s fill: addr=0x%0h, way=%b, blk_addr=%0d, data=0x%h\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_idx, line_idx, fill_data))
|
||||
end
|
||||
if (flush && ~stall) begin
|
||||
if (flush) begin
|
||||
`TRACE(3, ("%t: %s flush: addr=0x%0h, way=%b, blk_addr=%0d, byteen=0x%h, data=0x%h\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_idx, line_idx, dirty_byteen, dirty_data))
|
||||
end
|
||||
if (read && ~stall) begin
|
||||
if (read) begin
|
||||
`TRACE(3, ("%t: %s read: addr=0x%0h, way=%b, blk_addr=%0d, wsel=%0d, data=0x%h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_idx, line_idx, word_idx, read_data, req_uuid))
|
||||
end
|
||||
if (write && ~stall) begin
|
||||
if (write) begin
|
||||
`TRACE(3, ("%t: %s write: addr=0x%0h, way=%b, blk_addr=%0d, wsel=%0d, byteen=0x%h, data=0x%h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), way_idx, line_idx, word_idx, write_byteen, write_data, req_uuid))
|
||||
end
|
||||
end
|
||||
|
|
|
|||
25
hw/rtl/cache/VX_cache_tags.sv
vendored
25
hw/rtl/cache/VX_cache_tags.sv
vendored
|
|
@ -38,8 +38,6 @@ module VX_cache_tags #(
|
|||
input wire [`UP(UUID_WIDTH)-1:0] req_uuid,
|
||||
`IGNORE_UNUSED_END
|
||||
|
||||
input wire stall,
|
||||
|
||||
// init/fill/lookup
|
||||
input wire init,
|
||||
input wire flush,
|
||||
|
|
@ -75,7 +73,7 @@ module VX_cache_tags #(
|
|||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
evict_way_r <= 1;
|
||||
end else if (~stall) begin // holding the value on stalls prevents filling different slots twice
|
||||
end else if (lookup) begin
|
||||
evict_way_r <= {evict_way_r[NUM_WAYS-2:0], evict_way_r[NUM_WAYS-1]};
|
||||
end
|
||||
end
|
||||
|
|
@ -91,22 +89,17 @@ module VX_cache_tags #(
|
|||
.data_out (evict_tag)
|
||||
);
|
||||
end else begin : g_evict_way_0
|
||||
`UNUSED_VAR (stall)
|
||||
assign evict_way = 1'b1;
|
||||
assign evict_tag = read_tag;
|
||||
end
|
||||
|
||||
// fill and flush need to also read in writeback mode
|
||||
wire fill_s = fill && (!WRITEBACK || ~stall);
|
||||
wire flush_s = flush && (!WRITEBACK || ~stall);
|
||||
|
||||
for (genvar i = 0; i < NUM_WAYS; ++i) begin : g_tag_store
|
||||
|
||||
wire do_fill = fill_s && evict_way[i];
|
||||
wire do_flush = flush_s && (!WRITEBACK || way_idx[i]); // flush the whole line in writethrough mode
|
||||
wire do_fill = fill && evict_way[i];
|
||||
wire do_flush = flush && (!WRITEBACK || way_idx[i]); // flush the whole line in writethrough mode
|
||||
wire do_write = WRITEBACK && write && tag_matches[i];
|
||||
|
||||
wire line_read = (WRITEBACK && (fill_s || flush_s));
|
||||
wire line_read = (WRITEBACK && (fill || flush));
|
||||
wire line_write = init || do_fill || do_flush || do_write;
|
||||
wire line_valid = ~(init || flush);
|
||||
|
||||
|
|
@ -130,8 +123,8 @@ module VX_cache_tags #(
|
|||
) tag_store (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.read (line_read && ~stall),
|
||||
.write (line_write && ~stall),
|
||||
.read (line_read),
|
||||
.write (line_write),
|
||||
.wren (1'b1),
|
||||
.addr (line_idx),
|
||||
.wdata (line_wdata),
|
||||
|
|
@ -148,16 +141,16 @@ module VX_cache_tags #(
|
|||
`ifdef DBG_TRACE_CACHE
|
||||
wire [`CS_LINE_ADDR_WIDTH-1:0] evict_line_addr = {evict_tag, line_idx};
|
||||
always @(posedge clk) begin
|
||||
if (fill && ~stall) begin
|
||||
if (fill) begin
|
||||
`TRACE(3, ("%t: %s fill: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h, dirty=%b, evict_addr=0x%0h\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), evict_way, line_idx, line_tag, evict_dirty, `CS_LINE_TO_FULL_ADDR(evict_line_addr, BANK_ID)))
|
||||
end
|
||||
if (init) begin
|
||||
`TRACE(3, ("%t: %s init: addr=0x%0h, blk_addr=%0d\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_idx))
|
||||
end
|
||||
if (flush && ~stall) begin
|
||||
if (flush) begin
|
||||
`TRACE(3, ("%t: %s flush: addr=0x%0h, way=%b, blk_addr=%0d, dirty=%b\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(evict_line_addr, BANK_ID), way_idx, line_idx, evict_dirty))
|
||||
end
|
||||
if (lookup && ~stall) begin
|
||||
if (lookup) begin
|
||||
if (tag_matches != 0) begin
|
||||
if (write) begin
|
||||
`TRACE(3, ("%t: %s write-hit: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), tag_matches, line_idx, line_tag, req_uuid))
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue